LMK01801: Skew on between CG1 and CG2

Hello Michael,

The value on the table in the datasheet you mentioned shows only for the same divider case. 
My customer would like to know different divider case. 

Regards,
Oba

Oba-san,

We specify this value this way because we assume that the customer will be using the SYNC functionality offered by the device. Assuming that both output banks are phase aligned, the skew between outputs from different dividers is identically the same as it would be between outputs of the same divider that are not synchronized. 

If the banks are not synchronized, then the skew is not well characterized. But this use case is not recommended and not likely to be used by a customer.

Thanks,

Michael

Hello Michael,

So do you mean the value on the table can apply for different divider case? In the customer case, it is CLKout0~2 and CLKout4~6?

Regards,
Oba

Hello Michael,

Sorry for asking many times, but could you read the below post?

https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/859944/lmk01801-output-skew-between-different-divider

It says that ch8(CG3) and ch12(CG4) skew was +-16ps.
It looks a little bit different from the table.

How to think about it? Is it just because of difference of TYP and MAX ?
In this case, TYP should be also 3ps?

Sorry, I just want to avoid misunderstanding.
Are the skew within the same divider and the skew between different dividers really the same?
Even though the rising edge is aligned by SYNC function, I feel different divider circuit path could produce additional skew.
Is it well designed?

Regards,
Oba

Oba-san,

No problem. I read through the post and there was no mention of what the exact clock output formats were beyond "differential". This specification, rather than a particular driving format, makes me think that the engineer in the old forum was measuring skew between differential signals of differing formats. This would fall within the spec for mixed signal skews. Additionally, the divider output paths should be matched, and the two output banks are synchronized by adjacent bits in the same register. So there should be no considerable difference. I will consult with our designers to see what their perspectives are.

Thanks,

Michael

Hello Michael,

Did you get any feedback from designers?

Regards,
Oba

Hi Oba, 

They have not yet gotten back to me. I will follow up.

Thanks,

Michael