TLC555CALC: Time calculation monopluse duration

Suma,

Figure 5-9 in data sheet shows about 180ns propagation delay. TLC555 is not fast enough for sub 1us.

I will see if a fast comparator would work better. 

Suma,

I was thinking of a D flip flop, For VG1, a negative edge clock input would be needed. (could VG1 be inverted?)

D is fixed high, so VG1 clock starts Q out as mono pulse high. C1 charges, after 200ns (probably less to account for all prop delays)  U1 applies a active low clear to D flip flop. Shortly after Q out goes low and C1 discharges. Vref could be a resistive divider from 5V supply. 

Hi Michallick,

I didn't get the overall schematic what you want to explain. My requirement is i have negative pulse of duration 10ns as shown in the above image of VG1 i need to amplify out with positive pulse of 200ns. If you have any idea which circuit can implement this type design suggest me. 

Best Regards,

Suma

Suma,

I'm adding logic support to find a negative clock D FF solution.

Hello Ian,

Can you share me the spice model or working simulation of TPUL2G123.

Best Regards,

Suma D

Hi Ian,

My customer is interested in the simulation of TPUL2G123 is there any alternate way to do the simulation like equivalent part that has spice model or using IBIS model to do the simulation do help me sorting the issue. They are interested in the negative voltage can be detected by this component is they want check. Thank you for you are continuous support.  

Hello Ian,

Please, can you guide which tool can be used to simulate the IBIS model and circuit connection, if possible, to get understand of the circuit.

Best regards,

Suma

Hello Ian,

Thank you for helping me understand the IBIS model. 

Is there any IC similar to the TPUL2G123 that has a SPICE simulation model and can be used for our project?

Best regards,

Suma