Other Parts Discussed in Thread: LMX2594
Dear team,
Please fine the attached schematic of LMK04828B and LMX2594 clock generators. We are using zynq ultrascale+RFSOC device to communicate with LMK and LMX via SPI protocol. All signals related to LMK,LMX are mapped to PL side of FPGA and LMK register configuration is done via PS mode programming and SPI pins are tapped out via emio to PL. Inputs of CLk0 100MHZ, CLK1-10Mhz and Vcxo-160MHZ and 3V3 voltage rails are coming properly. Reset signal we are configuring as output(0x14A 06).
1. Have I to give Pull down on the board for Reset signal?
2.We are unable to get the output clocks from LMK in Dclock as well SDClock.
3.We are able to read and write the LMK registers data through the SPI interface
Please check schematic and TICSPRO Tics_100_10_245p76.tcs