Part Number: CDCE813-Q1
Other Parts Discussed in Thread: CDCE913
Hello!
I was reading a similar topic: https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1190722/cdce813-q1-vs-cdce913
But I still have some doubts.
I am currently designing a system with a cluster of PCBs connected between them in a daisy-chain basis, where a master clock is generated in the first PCB and propagated along them in this daisy-chain. My requirements for the clock are not very high (25-40 MHz, jitter similar to PCIe gen 2), but I am concerned about the jitter degradation in each step of the chain, so I planned to clean it with a simple PLL. Looking at CDCE813 and CDCE913, and the previous link, I am still confused about the "jitter cleaning" feature that appears in CDCE813 but not in the 913. Both seem to have the same internal PLL configuration (apart of the described maximum/minimum values for jitter, internal VCO frequency, etc), so the question is: CDCE813 does have any "special" configuration which makes it better for jitter cleaning than the 913?
Best regards and thank you in advance,
Adrián
