Hi,

I am using the LMK04832LVM evaluation board.
I changed the clock divider values from the default configuration to meet my requirements.
The clock distribution frequency is 3200 MHz.
I am not using all SYSREF outputs (SCLK_out).

Test Case 1 — Default Board Termination Settings

• CLKout0: 100 MHz — LVPECL / LCPECL, 240 ohms

• CLKout2: 50 MHz — LVPECL / LCPECL, 120 ohms

• CLKout8: 100 MHz — LVDS / HSDS

• CLKout10: 50 MHz — LVDS / HSDS

Result:

All of the above output clocks are phase-aligned.
The rising edges occur at the same time with zero measurable delay between channels.

Test Case 2 — Changed Termination for CLKout8

• CLKout8: 100 MHz — LVCMOS, 50 ohms
  (Default board termination changed from LVDS/HSDS to 50 ohms LVCMOS, similar to the hardware termination used for CLKout5.)

Result:

CLKout8 is not phase-aligned with the other outputs.
The LVPECL and LVDS outputs remain aligned with each other, but the LVCMOS output shows a timing shift and does not match the first rising-edge timing.

Requirement / Questions

1) LVCMOS Termination Suggestion

I need recommendations for the correct board termination method for LVCMOS so that all output clocks (LVPECL, LVDS, LVCMOS) remain phase-aligned with zero delay.
My requirement is that the first rising edge of every output clock should occur at exactly the same time.

2) SYNC Event Usage Clarification

Is the SYNC event used only for the synchronization of SYSREF clocks (SDCLK), and Device clock outputs (DCLK)?
Or is SYNC event required to align all clock formats as well?

3) Phase Alignment Across Multiple Output Formats

I want all device clocks to be phase-aligned, even if they use different output formats such as LVDS and LVCMOS.
Is this achievable through termination + SYNC + configuration, or is there a recommended method?

Thanks in advance for any guidance.