We run into spur issue of LMK5B12204RGZT.
Our XO_P=19.2MHz,XO_N with 220 ohm terminal.
Please provide a suit PLL parameter to fix the issue.
Hi Ray,
Can you share your .tcs configuration file and output frequency plan? I can take a look to see if any optimizations can be made, and double check that I can replicate the same spur issue on my end.
LMK05318B_ADRV9002_CLK_300MHz_20251217.tcsOutput frequency=300MHz,XO_P=19.2MHz,XO_N connect with to GND .
Hi Ray,
I was able to replicate the same performance on my end. It looks like the APLL1 loop filter settings got changed from the default, so I went ahead and reverted those back. It looks like the spurs are coming from the PLL2 fractional N divider settings. When I changed the APLL2 SDM to 1st order the spurs went away on my end. You could also try experimenting with different division values and PLL orders (for example, instead of using 10000/50000 as the fraction, you could set APLL2_DEN_MODE = 0, PLL2_NUM = 3355443, and PLL2_order = 3rd order).
I've attached my updated config below, let me know if this works on your end.
I don't have a simulation file, I just experimented with different APLL settings while measuring the 300MHz output on a phase noise analyzer. Unfortunately I didn't save a phase noise plot with my updated config file, but the 12kHz-20MHz jitter was around 150fs on my setup.