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LMK1D1208P: Input Voltage Specification

Part Number: LMK1D1208P
Other Parts Discussed in Thread: CDCLVD1204

Hello Support team,

I have a question regarding to the Specification of the LMK1D1208P Clock Buffer.

In the Date Sheet on Page 6 the Input Voltage is specified as followed 

| VIN,DIFF(p-p) Differential input voltage peak-to-peak {2 × (VINP – VINN)} |

| VICM = 1 V (VDD = 1.8 V) 0.3 2.4 VPP VICM = 1.25 V (VDD = 2.5 V/3.3 V) |

| MIN=0.3V  MAX=2.4V |

Why is the differential peak-peak Input voltage defined as 2 × (VINP – VINN)?

Isn't the differential peak-peak Input voltage defined as (VINP – VINN)? Where does the factor 2 comes from?

 

Why I am asking the question is that I want to connect the LVDS DC coupled output of CDCLVD1204 buffer with the DC coupled input of LMK1D1208P buffer.

Would it be possible?

 

Tank you for your support

 

  • Hi Waldemar, 

    Why is the differential peak-peak Input voltage defined as 2 × (VINP – VINN)?

    Isn't the differential peak-peak Input voltage defined as (VINP – VINN)? Where does the factor 2 comes from?


    Not exactly. 

    Differential peak to peak voltage is usually defined as the difference between the interpair i.e. _P & _N

    Take the following example: 

    For some people, the differential input peak to peak is Vss. 
    VID is typically the single ended input. This is my definition as well. 

    The factor of two comes when viewing or thinking about the differential waveform. If you subtract the _P & the _N signal - you full differential signal peak to peak is simply 2*VID or 2*(VIH-VIL). 

    There is no official industry standard. This was something that confused me when I started in clocks a few years ago as well as I saw the same acronyms have different meaning between different datasheets and vendors. 

    All that really matters is defining what the input spec is - in the case of LMK1D the differential peak-peak Input voltage is defined as 2 × (VINP – VINN) which leaves no error for confusion. 

    This is an issue between product lines as well because if you ask our HSC product line what VID is defined as - they argue it's the full differential swing i.e. 2*(Vin_p - Vin_N). 
    In the clock and timing PL, we usually consider VID to be the single ended input swing. 

    As mentioned, - as long as we define what the requirements are - everything is good. 

    Now for your second question, can DC coupled LVDS output of CDCLVD1204 buffer be DC coupled to input of LMK1D1208P? 
    The answer to that is yes. 

    In this case the minimum guaranteed swing is 250mV. 
    This is actually a typical LVDS driver given LVDS is the only signal format that is standardized in industry. 
    There requirements for the input of LMK1D1208P are as follows: 

    We need a minimum peak to peak differential input of 300mV or (150mV VID aka single ended) 

    From the LVDS output above (VOD) - we are guaranteed a minimum single ended output swing of 250mV. This 250mV guarantee meets the input requirements for LMK1D1208P. 

    Here is the input termination assuming a LVDS driver. 

    All you need is your standard 100Ohm differential termination near the receiver i.e. input pins of LMK1D1208P. 

    Best regards, 

    Vicente 

  • Hi Vicente,

    thank you very much for your quick support. I really appreciate it.

    The support is the reason I like using TI parts where possible.

    Now I can go on with my design.

    Thanks and have a nice day.

  • Hi Waldemar, 
    I am glad! We are always here to help Slight smile
    Have a great weekend. 

    Best regards, 

    Vicente