CDCE913: Regarding the Power-Up Sequence

Ryu Yamashita

Part Number: CDCE913

Hi team,

The recent datasheet update included changes to the power-up sequence.
Why was this modified?
I need to understand the impact on existing systems, so please explain the background for this change.

Best Regards,
Ryu.

6 months ago

0 Sandra Saba 6 months ago

TI__Expert 3810 points

Hi Ryu,

We recommend that the input clock to CDCE913 is running before VDD is on.

Best,

Sandra

0 Ryu Yamashita 6 months ago in reply to Sandra Saba

Genius 4845 points

Hi Sandra,

Thank you for your reply.
What I want to know is why the change was made.
Not how the change was made.

Best Regards,
Ryu.

+1 Sandra Saba 6 months ago in reply to Ryu Yamashita

TI__Expert 3810 points

Hi Ryu,

Sorry i misread the question.

In certain applications the PLL would not lock if the clock input was a static signal to avoid running into this issue ideally the input clock needs be on before VDD. Also avoid long delays between turning on the input clock after turning on VDD, keep the delay under 1 second.

Best,

Sandra

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CDCE913: Regarding the Power-Up Sequence