• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 22 subscribers
  • Views 150 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK5B33216: Config review

Daniel Waleniak
Expert 6425 points

Part Number: LMK5B33216
Other Parts Discussed in Thread: ADC3664

Dear Team,

We need some help in some understanding LMK5B33216 being used in a custom solution for a client with ADC3664. Input is intended to be 120MHz and output on all 16 channels to be 480MHz with XO 38.88 MHz.

 

The signal is used as LVDS clock for ADC3664.

 

Please find attached I2C configuration attached. We had some issues in loading the configuration with TICPRO-SW. We are configuring the IC usign I2C addresses.

 

Best regards,

Daniel Waleniak

lmk_config.txt 

 

 

 

 

  • 0
    TI__Expert 6425 points

    Dear Team,

    Any feedback? Please see additional information from the customer below.

    For the ADC3664, can you please clarify.

    1. Do you have multiple custom boards with 16 ADC3664 ICs on each board?
      1. How many boards are there?

    NS: We have 5 assembled boards with 16 ICs on each.

    1. Do only some ADC3664 ICs on each board observe the issue?
      1. And they do not appear related in terms of where they are physically located or where they are in the signal chain?

    NS: Yes, we observe on some ICs (not the same position per board).

    The LVDS clock is not being sent. That happens to one to two ICs per board.

    1. Can you share some oscilloscope (at min. input and output clock, power supply) screenshots showing working ICs and not working ICs?

    NS: This is the configuration process we are following, please expect oscilloscope images tonight:

          1. We do a power down so that we can perform configuration to the input clocks for ADC
            1. Command: 0x0008, 0x01
          2. After the clocks have been set, we configure ADC chips to send constant value and do power on
            1. Commands:
            2. //reset
    1. 0x0000, 0x01
    2. 0x0000, 0x00
            1. // output mapping
    1. 0x0007, 0x40
    2. 0x0007, 0x48
    • 0x0007, 0x4b
            1. // load efuse (wait to finish) – here we make a pause also like described in datasheet
    1. 0x0013, 0x01
    2. 0x0013, 0x00
            1. // change LVDS delay
    1. 0x001E, 0x00
            1. // powerdown FCLK
    1. 0x0009, 0x20
            1. // config_resolution
    1. 0x001b, 0x80
    2. 0x001b, 0x88
            1. // config decimation bypass (default)
            2. // config fclk
    1. 0x0019, 0x10
            1. // config CONST pattern
    1. 0x0014, 0x30
    2. 0x0015, 0x33
    • 0x0016, 0x6F
            1. // power on
    1. 0x0008, 0x00
          1. During the calibration of LVDS on FPGA side we do communication with ADC IC (until calibration is completed) where we set following registers:
            1. // const for delay calibration
    1. 0x0014, 0x30
    2. 0x0015, 0x33
    • 0x0016, 0x6F
            1. // const for lane 0 bitslip
    1. 0x0014, 0x50
    2. 0x0015, 0x55
    • 0x0016, 0x6D
            1. // const for lane 1 bitslip
    1. 0x0014, 0xA0
    2. 0x0015, 0xAA
    • 0x0016, 0x6E
          1. After the calibration is done, we write following register to set to input sampling
            1. 0x0016, 0x02

     

     

    Best regards,

    Daniel

  • 0 in reply to Daniel Waleniak
    TI__Expert 3285 points

    Hi Daniel,

    Could you share .tcs config file for LMK5B33216?

    Best,

    Riley