• State TI Thinks Resolved
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 21 subscribers
  • Views 156 views
  • Users 0 members are here
Support feedback
Options
Options
Related

LMX2694EPEVM: SYSREF Mode

TI-CSC
Genius 15085 points

Part Number: LMX2694EPEVM

Hello E2E experts,

We have procured an LMX2694EPEVM evaluation board for prototyping.

We would like to test SYSREF mode, as indicated in the user manual (p8 figures 9 and 10), by generating a signal on RFOUT B with a programmable delay (relative to RFOUT A), but we are unable to generate this output signal. Figure 10 does not show the signal frequency either (are we really at 100MHz output? With an OSCIN also at 100MHz?).

Our problem is that when we reproduce the PLL settings shown in Figure 9 as example, as soon as VCO_PHASE_SYNC is activated, the RFOUT A output unlocks (the output frequency is no longer 100MHz). The RFOUT B output remains off (no signal). Pressing ‘toggle SysRefFreq Pin’ or ‘Toggle Sync Pin’ causes the USBtoANY module to send only a high state (rising edge) but seems to have no effect on the RFOUT A and RFOUT B outputs.

Can you confirm the hardware configuration and specify whether an external signal is required on the SYNC pin and/or SYSREF? (if the USBtoANY module is sufficient for this case).

Can you send us a configuration file for all the registers to ensure that the test is reproducible?

If possible, please show us a timing diagram for the SYNC, SYSREF, RFOUTA and RFOUTB signals so that we can validate our setup.

Regards,

TICSC

  • 0
    TI__Guru** 114140 points

    Hi There,

    After checking the VCO_PHASE_SYNC bit, the N divider will change, we may need to program all register again.

    The INPIN_IGNORE bit needs to be unchecked otherwise the signal at SYNC and SYSREFREQ pin will be ignored.

  • 0 in reply to Noel Fung
    TI__Genius 15085 points

    Hello Noel,

    I went through the recommendation to disable (=0)  the INPIN_IGNOR , but I still facing the same issue. 

    As soon as I activate VCO_PHASE_SYNC = 1, the RFOUTA output signal unlocks.

    However, I notice that I get an error when I activate ‘toggle SysRefReq Pin’: Python Error Pin ‘SysRefReq’ not found
    (this error does not appear for ‘toggle Sync Pin’). It could be related to my issue ?

    For information enclosed there are

    - screenshots of the error on TICS Pro SW
    - Register table
    - Oscilloscope signals on RFOUTA (green), RFOUTB (orange), and OSCIN (yellow) before and after activation of VCO_PHASE_SINC

    Fullscreen 4705.HexRegisterValues.txt Download 
    R114	0x720000
R113	0x710000
R112	0x70015E
R111	0x6F0097
R110	0x6E0448
R109	0x6D0000
R108	0x6C00F1
R107	0x6B0000
R106	0x6A0007
R105	0x694440
R104	0x680000
R103	0x670000
R102	0x660000
R101	0x650000
R100	0x640000
R99	0x630000
R98	0x620000
R97	0x610000
R96	0x600000
R95	0x5F0000
R94	0x5E0000
R93	0x5D0000
R92	0x5C0000
R91	0x5B0000
R90	0x5A0000
R89	0x590000
R88	0x580000
R87	0x570000
R86	0x560000
R85	0x550000
R84	0x540000
R83	0x530000
R82	0x520000
R81	0x510000
R80	0x500000
R79	0x4F0000
R78	0x4E0064
R77	0x4D0000
R76	0x4C000C
R75	0x4B0A80
R74	0x4AF000
R73	0x4906E4
R72	0x480000
R71	0x470058
R70	0x46C350
R69	0x450000
R68	0x4403E8
R67	0x430000
R66	0x4201F4
R65	0x410000
R64	0x401388
R63	0x3F0000
R62	0x3E0322
R61	0x3D00A8
R60	0x3C0019
R59	0x3B0000
R58	0x3A0001
R57	0x390020
R56	0x380000
R55	0x370000
R54	0x360000
R53	0x350000
R52	0x340420
R51	0x330080
R50	0x320000
R49	0x314180
R48	0x300300
R47	0x2F0300
R46	0x2E07FE
R45	0x2DC0C0
R44	0x2C0001
R43	0x2B0000
R42	0x2A0000
R41	0x290000
R40	0x280000
R39	0x2703E8
R38	0x260000
R37	0x258104
R36	0x240020
R35	0x230004
R34	0x220000
R33	0x211E21
R32	0x200393
R31	0x1F43EC
R30	0x1E318C
R29	0x1D318C
R28	0x1C0488
R27	0x1B0002
R26	0x1A0DB0
R25	0x190624
R24	0x18071A
R23	0x17007C
R22	0x160001
R21	0x150401
R20	0x14D048
R19	0x132797
R18	0x120064
R17	0x11012C
R16	0x10015E
R15	0x0F064F
R14	0x0E1E70
R13	0x0D4000
R12	0x0C5002
R11	0x0B0018
R10	0x0A10D8
R9	0x090604
R8	0x082000
R7	0x0700B2
R6	0x067802
R5	0x0503E8
R4	0x040E43
R3	0x030642
R2	0x020500
R1	0x010809
R0	0x006018

    Regards,

    TICSC

  • 0 in reply to TI-CSC
    TI__Guru** 114140 points

    Hi There,

    The unlock with VCO_PHASE_SYNC = 1 is due to the phase detect frequency being too high when IncludedDivide = 6, we can use the FCAL_HPFD_ADJ register to reduce the phase detector frequency being used during VCO calibration to less than 50MHz.

    Right, I see the same python error on my side, I will fix this. In the meantime, go to the User Control page to manually set the SYSREFREQ pin state.