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Original question:

LMK04832: SYNC issue and some detail expansion

LMK04832: SYNC issue and some detail expansion2

Yuxi Liu(Tony)
Expert 3980 points

Part Number: LMK04832

Hi TIer

To follow up this issue:

https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1608730/lmk04832-sync-issue-and-some-detail-expansion/6206745

We still want to confirm that SYNC_EN is selected SYNCPinDisabled and SYNC_DIS is selected. Why the external state of SYNCpin affects the state of alignment. The test results are as follows, and the tcs file is configured as follows:

sync_en dis off_pin dis.tcs 

When SYNC_PIN = low level or High-Z , Repeat the test approximately multiple times, with occasional misalignment. 

When SYNC_PIN = high level , Tested hundreds of times and did not appear.

What might be the reason for this probabilistic deviation

  • 0
    TI__Genius 14361 points

    Hi Tony,

    I took this setup into lab to try to replicate it myself. Using your configuration file and an LMK04832EVM, I did not see any deviation. I applied both high and low levels to the SYNC pin and saw no change in behavior. Can you provide more information about your hardware setup?

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    TI__Expert 3980 points

    Hi Michael

    We make a video to show the issue.

    Please check. 

    3 channels of clock rising edge signals are being sampled on the oscilloscope. The multimeter shows the SYNC PIN low level, the customer re-triggers the EVM and outputs the clock signal by clicking the configuration button of the GUI multiple times.

    We can see that

    1. The rising edges of the 3 channels do not in same time.

    2. At the last trigger, the yellow curve is abnormally advanced by about 300 ps, which is what we say. 

  • 0 in reply to Yuxi Liu(Tony)
    TI__Genius 14361 points

    Hi Tony,

    So, just to clarify, you only see the misalignment issue occur when the SYNC pin is low level? This is an issue with which I am unfamiliar. I will look into our collateral and get back to you Monday.

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    TI__Expert 3980 points

    Hi Michael

    Yes, this happens when I change the SYNC PIN to low or Hi-Z after I connect the SYNC PIN with an FPGA, but it doesn't happen when the SYNC PIN is set to high. Please help check, thank you very much. 

  • 0 in reply to Yuxi Liu(Tony)
    TI__Expert 3980 points

    Hi Michael

    Could you give some suggestion? Thank you very much.