LMK3H2108: Phase noise plot

Hi Kei,

It looks like the image you attached didn't upload properly. If you're referring to the phase noise spurs at higher frequencies for the LP-HCSL outputs, the reason for this behavior is due to the device's fractional output dividers, which enable more flexible fractional frequencies at the cost of these fractional spurs.

If this is not what you're referring to, let us know which datasheet figure you are asking about and we can help you further. 

Best,
Jaryd

Hello Jaryd-san,

Thank you for the answer.
Yes, that's what I was reffring to.

The customer would like to input this clock (100MHz) to FPGA, and they are worried about the negative effect of this fractional spurs.

Is there any concern of fractional spurs for clocking FPGA?

Best Regards,
Kei Kuwahara

Hi Kei-san,

As long as the device meets the customer's RMS jitter requirements it should be ok. The spurs seen in the datasheet are likely acceptable for FPGA applications, but it would be best to check the FPGA jitter requirements to ensure proper functionality.

Best,
Jaryd

Hi Kuwahara-san,

Per e-mail. Please share the FPGA requirements

Alternatively customer can test device with FPGA if they dont want to share the requirements 

Best,

Sandra 

Hi Sandra-san, Jaryd-san,

Thank you for the reply.

The phase noise requirement is -110dBc/Hz at certain offsets frequency from the carrier.
Those spurs are not at the exact point of the specification of FPGA, but some spurs are bigger than -100dBc/Hz.

Are those spurs going to affect FPGA?

Best Regards,
Kei Kuwahara

Hi Kuwahara-san,

Since we do not know the FPGA internal structure, we cannot say certainly whether or not these spurs will affect your FPGA performance. This depends on the FPGA, so it would be best to reach out to the FPGA vendor with this question as they have more information about the FPGA itself.

Best,
Jaryd