CDCM7005RGZT Reference Clock sine wave to Square wave conversion

Hi Kiruba,

In this case, the jitter contribution from the comparator itself will be masked by the timing uncertainty (jitter) generated by the input signal slew rate (SR) as it crosses the comparator's switching threshold window (hysteresis).  Input slew-rate limited jitter can be expressed theoretically as: J_in = V_hyst / SR. 

As input slew rate is increased high enough, the impact of J_in will be minimized until eventually the comparator's thermal noise will limit the jitter performance.  However, this will not be the case in your situation as explained below.

For a 10-MHz, 0-dBm sine wave source, the slew rate will be about 17 V/us based on a 10%-90% rise time of ~30 ns.  The typical input hysteresis voltage of the LMV7219 is 7 mV .  So we can estimate the slew-rate limited jitter as: J_in = 7 mV / (17V/us) = 400 ps!  This is very large and should dominate any jitter that could be contributed from the comparator's noise.  This will be the case with other sine-to-square wave conversion devices, like schmitt-trigger buffers, which can have even larger hysteresis and thus more jitter.

The CDCM7005 is a jitter cleaner, so assuming you design with a narrow closed-loop PLL bandwidth, the PLL will suppress the high phase noise of your reference input squarewave at frequency offsets above the loop bandwidth and the output clock phase noise will follow the low phase noise profile of the external VCXO.

Best regards,
Alan