Part Number: LMK04616
I have a board with LMK04616 and a 100 MHz fixed frequency oscillator (CCLD-033) connected to the OSCin port. This is design choice of an external hardware vendor, so don't ask me about that.
There can be 2 variants for the output frequences:
- 1000/250 MHz with Prescaler=6, and N=10,
- 1200/300 MHZ with Prescaler=5 and N=12
The lower frequency would be obviously produced by 4 divider in the output blocks.
Firstly I need help to get the required signal flow (that is Input stages and PLL1 completely disabled and bypassed:

It is not always clear what the "enable buffer" in the register maps exactly refer to.
Secondly I need help in configuring the loop filter for the 2 frequency variants. I do not have a great idea about that and the Data Sheet directly advises "to contact TI with the application requirements to get the optimized loop filter settings".