LMK04828: LMK04828 LOCK ISSUE

Hi Ray,

Your schematic picture is too small, I can hardly read.

is the 10MHz input clock sine wave? If this is the case, the unlock could be due to the low slew rate of this 10MHz clock. 

The other problem in your configuration is, PLL1 fpd is just 80kHz, which is too low. If your VCXO Vtune pin input impedance is also low, then PLL1 may not lock. Suggest change fpd to 1MHz (you may need to re-design the loop filter).

• Thanks for feedback.I sent the schematic by E-mail for your review.

Here is my additional questions:

1. There is a clock buffer between the ocxo and lmk04828. Sine wave may not be the issue.
2.How to increase the Fpd in the following case?
Reference clock=10MHz
Vcxo=122.88Mhz
Output clk=491.52MHz/245.76MHz
3.How to design pll1 in TICSPRO

Hi Ray, 

Closing this post as we have taken it offline.