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LMK00334: Impact of Output Clock mapping to devices with different logic levels

Part Number: LMK00334
Other Parts Discussed in Thread: AM6442

Hello Team,

Could you please help on below query asap.

I am using LMK00334 clock buffer in one of our design to configure 3x HCSL outputs.
Input CLK is HCSL and 3x outputs also required in HCSL 
I tied the VCCOA,VCCOB pins to 3.3V.
My design requirement is as follows.
1) CLKoutA0 & CLKoutA0* will be mapped to a device whose REF_CLK input is compatible to 0V to 2.7V.
2) CLKoutB0 & CLKoutB0* will be mapped to a device whose REF_CLK input is compatible to 1.8V.
3) CLKoutB1 & CLKoutB1* will be mapped to another device whose REF_CLK input is compatible to 1.8V.

Will there is any issue, when mapping the 3.3V compatible output clocks of LMK00334 to devices which is compatible to either 2.7V or 1.8V?

NOTE:-If there is any issue, please suggest some recommendation to overcome this issue with same configuration needs.