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CDCLVP1102: CDCLVP1102 to Artix ultrascale+ LVDS input

Hamed Sotoudi Namin
Prodigy 20 points

Part Number: CDCLVP1102

Dear Sir/Madam,

in our project we used CDCLVP1102 as input trigger interface to the FPGA. As the chip is LVPCEL it is powered with 3.3V and the FPGA bank is powered with 1.8v. According the FPGA documents , the LVDS IVDiff is minimum 100mv and nominal 350 mv. The output of the CDCLVP1102 is pulled down to GND with a 150 ohm resistor and there is a series resistors 70 ohm to the fpga to reduce the swing from 600 mv to 350mv according to https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/870502/cdclvp1102-lvpecl-to-lvds?tisearch=e2e-sitesearch&keymatch=CDCLVP1102#

there are also two ac-coupling 100nf capacitors to block dc bias. The FPGA inside DC bias and 100 ohm termination is activated. 
when there is no signal in the input of the chip ( it is ac coupled input) the output of the chip is noisy and it fluctuates more than 100 mv that is why in the FPGA a random pulse is generated . 
when I connect a pulse to the input, at the FPGA pins I measure the pulse but still the IBUFDS in the FPGA generates a random pulse. ( the pulse frequency is very low )

when the input of the chip is several KHz square wave, the result is the same. 
when the input of the chip is above 1 MHz square wave, I receive a clean sqaure wave with the same frequency.

I would like to ask why the output of the chip fluctuates more than 100 mv when there is no signal or less than 1 MHZ singnal. Is there anything which we have overlooked in our design?

I would like to thank you for your help and support in advance.

many regards,

Hamed Sotoudi

  • 0
    TI__Genius 17251 points

    Hi Hamed,

    Can you share more about how you are terminating the input to the CDCLVP1102?

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Prodigy 20 points

    Hi Srinivasan,

    here is the schematic which I think makes description easier

    The input is AC coupled single ended and both P and N are DC Biased.
    According to this page CDCLVP1102: Single-end clock input I assume the input should be fine.
    The output is terminated and DC biased on the FPGA side after the capacitor ( inside the FPGA, I even tested with external termination)
    Even with no input connected, I see a random pulse detection in the FPGA using the chip scope. With the oscilloscope I see the swing around 100 mv ( and more) at the output.
    When I connect a rectangular signal, above the 10k frequency everything works perfect, below it there are many detected random pulses.
    We are going to use it for pulses ranging from 100 Hz to several KHz and some application 1MHz.

    regards,
    Hamed

  • 0 in reply to Hamed Sotoudi Namin
    TI__Genius 17251 points

    Hi Hamed,

    I suspect that the DC block may be the reason you are unable to see your low frequency signals output without issue. Can you try DC coupling the input?

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Prodigy 20 points

    Hi Michael,

    I will try and let you know. But I would like to add, that even without any thing connected to the input, FPGA generates random signal. I checked the output of CDCLVP1102 it swings randomly around 150 mv.

    Regards Hamed

  • 0 in reply to Michael Srinivasan
    Prodigy 20 points

    here is the result after removing the AC coupling Capacitors.
    the Bias voltage on the Chip is 2v
    The Bias on the FPGA input is 1.2 V
    The termination is on the FPGA side is 100 ohm
    1- The input signal for test is 20KHz rectangular signal with 1% duty cycle

    there is one unwanted pulse detected
    2- 20khz rectangular signal with 10% duty cycle


    3- 5KHz pulse with 30 ns pulse width

    4- 5 MHz pulse with 30 ns width


    5- Input is disconnected and there is no signal fed to the Chip.


    which there are many unwanted signals.
    Actually in the idle time which there is no signal connected to the chip, it is expected no output and zero. But the chip output generates random signal ( fluctuates around 100 mv or even more) which is detected by the FPGA lvds as valid signal.

    when I created a 50 mv dc bias difference at the FPGA input ( the P side is 1.080 v and N side is 1.13 V) it works fine even with 1 HZ pulse

  • +1 in reply to Hamed Sotoudi Namin
    TI__Genius 17251 points

    Hi Hamed,

    The biasing at the input is the reason for the chatter you are seeing. When the device is not in use, having this biasing will result in chatter at the output - the input will be very sensitive to any voltage difference, and you will see the output behavior you are seeing. 

    The appropriate course of action would be to do what you have done with the biasing - if you could apply that to the input, the outcome would be the same. There needs to be a set difference to ensure no toggling.

    Thanks,

    Michael