LMK5B33414: Question about LMK5B33414

Hi Jimmy, 

The datasheet phase lock time of 38 seconds assumes a phase error of up to 100ns, but in the attached configs the phase lock threshold is set to around 1.85 ns. Since the phase lock threshold is much more strict it will take longer to achieve lock. 

To ensure reliable operation for 1pps ZDM, I usually recommend this exact sequence:

1. Load config (write all registers in TICS Pro GUI, or run start-up programming sequence from "programming" tab in GUI)

2. Toggle SYNC_SW bit by writing R21 = 0xE1, then R21 = 0xA1

3. Toggle SWRST bit by writing R23 = 0x40, then R23 = 0x00. 

This sequence should ensure that the TDC, channel dividers, SYSREF dividers, etc. are all synchronously reset which should help the device achieve lock to 1pps when ZDM is enabled. Let me know if this helps

Hi Connor,

As shown in the attached image "threshold", we have previously attempted to set the threshold to a condition greater than 118ns. We were unable to adjust it precisely to exactly 100ns, I don't know why this is the case? My operation steps are as follows: After the system is set up, first load the configuration file "LMK5C33414A, 48 MHz XO, 1PPS IN0, 1PPS OUT0-2_118ns_threhold" in the attached file. According to your suggestion, generate the programming sequence under the "programming"

menu and then write it to the device, as shown in the attached image "programming". Then click the "soft-reset and sync" button, as shown in the attached image "swrst_sync". because I cannot manually set the RAW registers menu as shown in the picture "reg_write_failed" in the attachment. The total locking time ended up being approximately 3 minutes,as shown in the attached image "status".

Is there any way to keep the phase difference of input and output 1PPS signal unchanged, or have a small change(ns level) during each power cycle, without ZDM enabled? Image "Debug DPLL Phase Lock" is the description found in application note "The Debug Guide for Network Synchronizers (Digital and Analog Phase-Locked Loops)".We find the phase difference change a lot without ZDM now.

 From the table in datasheet which I captured, same output frequency will have differenet jitter with post divider enabled or disabled. It seems enable post divider will be better than using channel divider only, for jitter performance. Could you confirm this for me, and what is the reason.

Hi Anita, 

The DPLL phase lock threshold is calculated as something like (2^DPLL3_PL_THRESH) * VCO frequency * constant scaling factor, so it's not possible to set the phase lock/unlock threshold to any arbitrary limit. 

Instead of writing the raw registers to toggle SYNC_SW and SWRST, you could also check/uncheck the check boxes on the "SYNC/SYSREF/1-PPS" page which should have the same effect. 

Can you confirm if increasing the phase lock threshold reduced the lock time to around 3 minutes with or without ZDM enabled? There isn't a straightforward way to guarantee phase determinism between the input and output clocks across power cycles without using ZDM. 

It is expected for the output clocks to have better jitter performance when only the post divider is used and the channel dividers are bypassed. The post dividers and channel dividers have slightly different structures, and the post divider contributes less additive noise compared to the channel divider. 

Hi Connor,

Yes, I have tried check/uncheck the check boxes on the "SYNC/SYSREF/1-PPS" and found that it has the same effect as clicking "Soft-reset and sync". The test I described was conducted under the condition of NO ZDM. You can load my config to check. Enable ZDM it will take more than 40 minutes to lock. Changing this threshold has a relatively minor impact on the locking time. As I had previously set it at 1.85ns, and changed it to 118.35ns, the locking time remained around

3 minutes. This is inconsistent with what is described in the data sheet and cannot achieve the 38-second lock time.Is there something wrong with my config? What other factors can affect the lock time?

For divider addtive jitter:

 From you explained in the reply, could I assume each divider will add some additive jitter.

So the jitter performance will be something like: use post-divider only < use channel divider only < combination of post-divider and channel divider

Hi Anita, 

Makes sense, thanks for the clarification. The LMK5B has an additional phase lock timer which will prevent the LOPL status from clearing until a certain number of TDC cycles have elapsed. This is meant to prevent any false-positive readings for the phase lock status. The spec in our datasheet is measuring the input/output phase directly on an oscilloscope instead of using the device's internal monitoring features. I believe this explains why it takes around 3 minutes to lock without ZDM, but I would expect that the lock time should be similar even when ZDM is enabled. I tried loading your ZDM config and on my setup it looks like the DPLL is saturating. I'll have to look into this further to see what exactly is causing this, but in the meantime I've uploaded another 1pps ZDM config that I've confirmed works on my setup. 

Regarding your comment about the additive jitter from the dividers, yes that is correct. 

8244.LMK5B-ZDM-1pps-Working.tcs