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CDCS503: CDCS503 input clock specifications – pk‑pk jitter and duty cycle guarantee

Ryu Yamashita
Genius 4915 points

Part Number: CDCS503

Hi team,

Background:
We are evaluating CDCS503PWR with a 3.3‑V LVCMOS input clock.
After reviewing the datasheet (SCAS872) and related TI E2E threads, we could not find explicit guaranteed limits for input clock pk‑pk jitter or duty cycle.
Questions:
  1. Does TI define any guaranteed maximum input clock jitter (pk‑pk or RMS) for CDCS503PWR to ensure PLL lock and specified performance?
  2. Is there a guaranteed or recommended input duty‑cycle range (min/max %) for the LVCMOS input?

Best Regards,
Ryu.

  • 0
    TI__Expert 4240 points

    Hi Ryu,

    we will get back to you by the end of the week.

    Best,

    Sandra 

  • +1
    TI__Expert 3830 points

    Hi Ryu,

    To answer your questions:

    1. We do not specify the maximum input clock jitter for the CDCS503. What are you expecting your input jitter to look like? Are you observing that the jitter is a deciding factor as to whether the PLL locks or not?
    2. The output duty cycle range specified in the datasheet was determined given an input with 50% duty cycle. We don't have a specified range for input duty cycle for this part.

    Best,
    Jaryd

  • 0 in reply to Jaryd Dukes
    Genius 4915 points

    Hi Jaryd,

    Thank you for your reply.
    I have a few more questions.
    Is there an allowable tolerance range for the duty cycle (for example, 45–55%)?
    Also, how much variation in the input frequency is permitted?
    If 12.5 MHz is applied as the input, approximately what percentage of variation is acceptable?
    In addition, if the input varies, will it cause disturbances in the output?
    Best Regards,
    Ryu.
  • +1 in reply to Ryu Yamashita
    TI__Expert 3830 points

    Hi Ryu,

    We unfortunately do not specify a tolerance for the input duty cycle range. Given an 50% input duty cycle, we specify that the output duty cycle range varies 45-55%. As long as your output duty cycle falls within this range, your input duty cycle should be acceptable.

    The amount of variation you'll see depends on whether you're using the CDCS503 as a buffer or as a multiplier. If you're using it as a buffer, the output frequency will track the input, so the input variation will be roughly the same at the output. If you're using it as a multiplier, then input variation will be scaled to the output according to what multiplier value is set (4x for the CDCS503).

    The acceptable amount of variation depends on your use case and what jitter and PPM drift your application can tolerate.

    Best,
    Jaryd