LMK05318B: PPS synchronization with LMK05318B

Hi John,

For a 1-PPS input to synchronize with a 1-PPS output, the LMK05318B has a feature called pseudo zero-delay mode that provides phase determinism between a 1-PPS PRIREF clock input and a 1-PPS OUT7 output clock. In your application, the 8MHz clock would need to be moved to SECREF and used as a backup reference while the 1-PPS GNSS receiver signal is applied to PRIREF. This feature can be used to align the OUT7 output clock edge with the PRIREF input for

every sync event.

If you're synchronizing this way, the input-to-output phase delay can be minimized to be within ± 1 VCO cycle. More information about pseudo ZDM can be found in the LMK05318B datasheet section 8.3.16.

Additionally, if you need phase determinism on your other non-1-PPS outputs as well, we suggest designing with the LMK5B33216 or LMK5C33216A.

Best,

Jaryd

Thanks, Jared!  So to be clear, all our outputs would still be locked to the 8 MHz reference via SECREF, while PRIREF serves only to synchronize one output at a 1 Hz rate?  If so, that could be exactly what we need..

And in this case, would the GNSS PPS need to be provided continuously, or do you just apply the sync once?  If you sync continuously, would jitter on the GNSS PPS be transferred to the 1 Hz output?  (The whole idea is to have a low-jitter PPS that is sync'd to GNSS time.)

Thanks!

Hi John,

Unfortunately you cannot lock to both PRIREF and SECREF at the same time, so your other outputs would lock to the 1-PPS PRIREF and switch to SECREF only if PRIREF is no longer available.

Looking a bit closer at your design and the LMK05318B, I noticed that our reference input R-divider is 16-bit, meaning that the device cannot simultaneously handle a 1-PPS on PRIREF and 8MHz on SECREF. The TDC frequency of the DPLL would need to be 1Hz for the 1-PPS input, and the 16-bit R-divider can only divide the 8MHz down by 2^16=65,536. Apologies for not pointing this out previously.

As a remedy for this, I would suggest using the LMK5B33216 or LMK5C33216A and using separate DPLLs for each input frequency (1-PPS and 8MHz). This would allow the 1-PPS output to lock to the 1-PPS input while the rest of your frequencies can lock to the 8MHz input. To achieve the lowest jitter on the output that's sync'd to GNSS time, you can use the high-performance BAW PLL to output 1-PPS (APLL3 for the LMK5B, APLL1 for the LMK5C).

Best,

Jaryd

Thanks, Jaryd! 

So it sounds like what's really happening in that case is that the DPLL is running with the 1 PPS reference frequency to generate all outputs.  I suspect that would require a much longer loop time constant and consequently better TCXO to maintain performance.

Unfortunately it seems like this function isn't intended to do what we really want for our application.  However, we have an alternative PPS sync approach using hardware outside the LMK chip that we should do what we need.

Thanks for the quick responses!.