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CDCEL937: Frequency Resolution

Glen Alvis
Prodigy 20 points

Part Number: CDCEL937
Other Parts Discussed in Thread: CLOCKPRO,

We are using the CDCEL937PWR as a baud rate generator for RS422 communication.  It has 9 outputs but I only need 6.  Our design consultant has chosen either a 100MHz or a 29.49MHz clock as the input frequency.  Unfortunately if one of these two is chosen it cannot be changed.  I have downloaded the ClockPro software and I am having trouble acheving the baud rates that I require.

Here are the baud rates (yes, they are slow):

1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200

Can they be obtained with the CDCEL937PWR?

  • 0
    TI__Expert 3990 points

    Hi Glen,

    We're looking into your inquiry, we will get back to you early next week.

    Best,

    Jaryd

  • 0
    TI__Expert 3990 points

    Hi Glen,

    Unfortunately the baud rates you are trying to achieve do not seem to be possible with the CDCEL937. This device has 7 outputs with an input frequency range of 8-32MHz, so only the 29.49MHz input would work. The output dividers are 7-bit (with one 10-bit divider) and the VCO frequency range is 80-230MHz, which doesn't allow sufficient margin to generate any of the baud rates you've listed below 38400.

    We may have other devices in our portfolio that could work based on the requirements of your system. Could you let us know the following:

    • Are you expecting our clock to provide the baud for your application, and would you be ok with a 2-part solution (i.e. clock gen + buffer)?
    • What are your jitter requirements for your application?
    • Are you looking for programmable baud rates, or are you looking to generate all the baud rates at the same time?

    Best,
    Jaryd

  • 0 in reply to Jaryd Dukes
    Prodigy 20 points

    Thanks Jaryd!

    Here are the answers to your questions:

    I have been given "new" information, the 29.49MHz clock goes to an FPGA (XCAU15P...) and then to theCDCEL937 and out of the CDCEL937 and then to the FPGA and then to provide the baud rate.  Hopefully, the FPGA can divide down the frequencies coming in and going out to provide the baud rates.  If not I will be asking more questions.  Thanks again!

    glen