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LMX2594: phase synchronization of 2 LX2594 output

Yoda Yukihide
Prodigy 10 points

Part Number: LMX2594

Question:
Could you please advise on the necessary settings and design considerations to achieve this design goal?

Our design goal:
 In the following hardware configuration, we would like to achieve phase synchronization by setting the final stage to 1638.4MHz and 4096M.
(Phase synchronization definition: Synchronization of 5 periods of 1638.4MHz and 2 periods of 4096M as below figure)
0cb9d899-31e2-467c-90e3-7c8b4b26db7c.png
 
 
We have confirmed via oscilloscope observation that the 102.4MHz input to PLL1/PLL2 is synchronized in current H/W.
Could you please advise on the necessary settings of LMX2594 and design considerations to achieve this design goal?

We have also attached our proposed settings in a below table, so we would appreciate it if you could check for any problems with these settings.

In particular, we would appreciate answers to the following:
1. Is it necessary to make the lengths from LMK00304S to PLL1/PLL2 equal?
2. Is synchronization possible even without using the Sync Buffer?
image.png
 
Setting Table
 
Register / Parameter PLL1 config PLL2 config Remarks / Common Conditions
OSC_2X 0 0 Doubler disabled
MULT 1 1 Multiplier bypassed
PLL_R_PRE 1 1 R pre-divider
PLL_R 1 1 R divider (fPD = 102.4 MHz)
PLL_N (R36) 96 80 N divider (Integer-N mode)
MASH_ORDER 0 0 Fractional disabled (Integer mode)
CHDIV (R75) code 2 (/6) code 0 (/2) Channel divider
SEG1_EN 1 1 Segment 1 enabled (*Verify for Config 2)
OUTA_MUX / OUTB_MUX 0 0 Channel divider output
OUTA_PWR 19 19 Output power setting
OUTB_PWR 29 29 Output power setting
OUT_ISET 0 0 Max output current setting
OUTA_PD / OUTB_PD 0 0 RFoutA / RFoutB output enabled
MASH_RESET_N 1 1 MASH reset released
POWERDOWN 0 0 Normal operation
RESET 0 0 Reset released
FCAL_EN 1 1 VCO calibration enabled
VCO_PHASE_SYNC 0 0 Phase sync disabled
RAMP_EN 0 0 Ramp (frequency sweep) disabled
MUXOUT_LD_SEL 1 1 MUXout pin: Lock Detect output
CPG 7 7 Charge pump current: 15 mA
SYSREF Disabled Disabled SYSREF output unused
INPIN_IGNORE 1 1 External input pin settings ignored
VCO Frequency 9.8304 GHz 8.1920 GHz Calculated value (Within 7.5 to 15 GHz range)
RFoutA / B Frequency 1.6384 GHz 4.0960 GHz Final output frequency
 
 
  • 0
    TI__Guru** 120540 points

    Hi Yoda-san,

    Synchronization is not needed as both frequencies belong to Category 1 sync configuration. However, VCO_PHASE_SYNC = 1 is still required as channel divider is engaged.

    After programming the devices, input/output phase is deterministic, no external sync signal is needed.

    Trace length for the 102.4MHz clock should be identical. 

  • 0 in reply to Noel Fung
    Prodigy 10 points

    Dear Noel

    Thank you very much.
    Your advice is very helpful.

    I have a follow-up question.

    Even after following your advice and enabling VCO_PHASE_SYNC = 1, we have found that our current circuit may be experiencing the following problems:
    1) 4096MHz and 1638MHz are not being generated accurately. The frequencies are higher than the target (potentially +8~16MHz higher than expected).
    2) 4096MHz and 1638MHz are not synchronized.
    *We do not yet have a high-speed oscilloscope, so we have not been able to measure the quantitative error.

    The setting is VCO_PHASE_SYNC = 1, and the other parameters are as shown in the table above.

    While investigating the cause, we found the following problem in our circuit:

    Possible problem:
    The CPOUT pin is not connected to the VTUNE pin.

    (The following diagram shows our circuit.)

    Question:
    1) What impact could the fact that the CPOUT terminal output is not connected to VTUNE have on our current design goals?

    2) Is there a setting that would allow us to achieve our design goals without any problems even if the output of the CPOUT terminal is not connected to VTUNE?

    3) Could you please check if there are any other problems with our circuit?

  • 0 in reply to Yoda Yukihide
    TI__Guru** 120540 points

    Hi Yoda-san,

    CPout must connect to Vtune via the loop filter, otherwise the pll is never locked. 

    Others are good, also need to make sure the exposed pad is connected to the ground plane.