Part Number: LMK1C1104
We have deployed design using LMK1C1104. We have observed the delay in clock output by some number of input clock cycles, which is causing some difficulties for our design.
Presumably, this is described by datasheet as t_start, t_1G_ON, t_1G_OFF.
Two questions:
- is that delay, in number cycles, deterministic? Like, it's always going to be 3 input clock cycles before output clock is present?
- Does LMK1C1104A, which I see is new, remove this behavior? This is very much preferable for us, if so.
