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LMK04610: selecting clock synthesis part

gurudatta p
Prodigy 20 points

Part Number: LMK04610
Other Parts Discussed in Thread: LMX2820, LMK04208

We have a requirement of clocking high speed ADC on an FPGA SoC Clock requirement are as follows:

1. Sampling clock for ADC: 2GHz or 4 GHz, 1 output

phase noise profile for 2ghz is:

   100hz -103.08
1khz -112.08
10khz -120.08
100khz -123.08
1mhz -143.08
10mhz -144.08
100mhz -164.08

At 4Ghz:

 

100hz -103.06
1khz -112.06
10khz -120.06
100khz -123.06
1mhz -141.06
10mhz -142.06
100mhz -158.06

 

1.SYSREF frequency pulsed: 250Mhz, 2 outputs    
2.SYNC clock: 500MHz, 2 outputs    
3.All clocks to be in sync    
4.We are planning to use a 10MHz OCXO with the following phase noise profile as the source clock

 

10hz -130
100hz -155
1khz -166
10khz -173
100khz -175

5.Also provide simulation files if possible

Please suggest a device for clock synthesis from your portfolio.

  • 0
    TI__Guru** 119790 points

    Hi There,

    To get the 2GHz or 4GHz clock for ADC, a RF synthesizer such as LMX2820 is needed.

    You can use a clock device such as LMK04208 to get the other clocks you need.

    You also need a 100MHz VCXO as the reference clock to the synthesizer in order to get the phase noise performance you need. 

    LMK04208 can generate the 250MHz and 500MHz clocks with the internal PLL/VCO.

    LMX2820 is the best synthesizer we have, it cannot completely meet your phase noise requirement. 

    At 2GHz output, we can do:

  • 0 in reply to Noel Fung
    Prodigy 20 points

    Hi Noel,

    1. were using Ocxo , were it placed on board itself and part number: KLNBNTE100MFNFCAB
    2. since it is on board can we bypass pll1 and connect it to pll2 will it improve overall phase noise??
    3.

    is above configuration is fine can  get good phase noise, and will there be internal coupling of 2ghz and 125mhz 
    where if i probe 2ghz signal will i get any 125mhz signal on top of it

  • 0
    Prodigy 20 points

    Hi Noel,

    1. were using Ocxo , were it placed on board itself and part number: KLNBNTE100MFNFCAB
    2. since it is on board can we bypass pll1 ad connect it to pll2 will it increase overall phase noise??

  • 0 in reply to gurudatta p
    TI__Guru** 119790 points

    Hi There,

    if you use 10MHz as the reference clock to the synthesizer, the max. fpd is just 20MHz. So the N-divider is 400 for 2GHz output. If you can use 100Mhz reference clock, N divider is 40. PLL in-band noise depends on the FOM of the PLL and the N-divider value. Higher N means higher noise. You cannot get the target phase noise with 10MHz input clock.