LMX2572LP: Recommended PFD_DLY_SEL and MASH_ORDER for low VCO frequency / low N divider

Hi,

I would like to confirm the correct settings for PFD_DLY_SEL and MASH_ORDER when using the LMX2572LP at the following output frequency.

We would like to generate:

According to Table 3. Minimum N Divider Restrictions in the datasheet, for fVCO < 4 GHz, the minimum N divider values are different depending on the MASH order.

In this case, the device is not operating in integer-N mode, because the N divider value is fractional.
However, the calculated N divider value is approximately 24.77, which is lower than the minimum N divider value for fractional-N operation, even for 1st-order MASH.

Therefore, our understanding is that the current setting below is not recommended:

As a possible solution, we are considering reducing the PFD frequency by changing the multiplier from 5 to 3:

With this setting, the N divider value satisfies the minimum N requirement for 3rd-order MASH when fVCO < 4 GHz.

Therefore, we believe the following settings would be appropriate:

Could you please confirm whether this understanding is correct?

Also, if there is a more recommended setting for generating 835.950 MHz with a 27 MHz reference clock, please let us know.

Best regards,

Conor