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CDCS503: The output oscillates even though there is no input.

Ryu Yamashita
Genius 4895 points

Part Number: CDCS503

Hi team,

The output shows a waveform even though the input is in a stable High or Low state.
Both the input and output are connected to an FPGA, and a 22ohm resistor is connected in series in the wiring.
No pull-up or pull-down resistors are connected.
Since the FPGA has an internal pull-up, I initially thought this would not be a problem, but I suspect that the lack of a pull-up between the FPGA and the input may be causing the issue.
Can the absence of a pull-up or pull-down on the input cause the output to oscillate?
If it is necessary to share the circuit and waveform, I would prefer to communicate via private message or email.
 
Best Regards,
Ryu.
  • 0
    TI__Expert 3680 points

    Hi Ryu, 

    We're looking into your inquiry, we will get back to you within the next few days. Feel free to send your configuration/scope readings via email, as this may help with debugging your issue. 

    Best,
    Jaryd

  • 0 in reply to Jaryd Dukes
    Genius 4895 points

    Hi Jaryd,

    Thank you for your reply.
    Since I do not have your email address, I have sent you a friend request.
    Best Regards,
    Ryu.
  • 0 in reply to Ryu Yamashita
    TI__Expert 3680 points

    Hi Ryu, 

    I have sent an email to your email address, so you should have mine as well. Please allow us some time to consider your questions. 

    Best,
    Jaryd 

  • 0 in reply to Jaryd Dukes
    TI__Expert 3680 points

    Closing this e2e post since this conversation has continued over email.

    For reference, this should be the expected behavior of the part. Internal to the CDCS503 is a PLL that stabilizes the output frequency and SSC capabilities of the part. In this part, the PLL does not have a holdover mode or input loss detection to mute the clock output, so when the input reference is disconnected the output will continue in an unstable, free-running mode. If you are looking to mute the output when there is no clock input, it would be best to pull-down the OE pin when the FPGA clock input is no longer being provided.