LMK5C23208A: Layout Review

Hi Abhishek,

We are looking into your schematic and layout, please allow us some time to review and we will get back to you as soon as possible. 

Best,
Jaryd

Hi Jaryd,

Thanks for the reply. Meanwhile can you please guide me how to make the clock configuration file for LMK5C23208ARGCR. It need to be done in TICS pro tool right. Please provide the support and necessary steps to proceed.

Regards,
Abhishek

Hi Abhishek,

Yes the configuration file can be made with TICS Pro. If you're using an EVM to test/evaluate the chip, you can use the LMK5C33216A EVM with the LMK5C23208A TICS Pro device profile since they use the same silicon core and pin layout.

The schematic looks good for the most part, here are my comments:

• I noticed the I2C pullup resistors are depopulated; since the design uses I2C, the pullups on the I2C lines are needed for I2C to function properly.
• Although you are not using IN0/IN1, VDD_IN needs to be connected to VCC for PD# to be pulled up. The ferrite bead is optional if IN0/IN1 are unused.

Here are my layout comments:

• Make sure to place the 0.1uF bypass capacitors near the supply pins of the device, and use wider polygons for the VDD lines.
• The layout is quite dense for such a large board, are you adding other parts to the entire board later?
• The differential traces need to be spaced to ensure there is 100Ω differential trace impedance across the signal pairs.
• If components are depopulated in the schematic, ensure they are also depopulated in the layout.
• This portion of the layout appears to be incomplete, please double-check the routing of OUT5

Best,
Jaryd

Hi Jaryd,

Thanks for the reply.

For the LMK clock IC configuration, I don't have LMK EVM with me. I'm planning to configure my on-board LMK IC using TICS pro tool. In this case how should I configure the clock to the IC.

Please explain the procedures on how should i configure the APLL and output clocks for my required outputs

In schematics, since I'm using only XO input, I'm not using DPLL that's why i had not populated the parts for VDD_IN0 and VDD_IN1. As you mentioned the #PD pin needs pull-up. Instead of VDD_IN can i populate the external pull-up resistor for PD signal. Please suggest which is best - external pull-up or internal VDD_IN.

Also I2C lines are pulled up later in the schematics while going into the FPGA since the 3.3V signal level is converting into 1.8V

Regards,

Abhishek

Hi Abhishek,

Abhishek Manoj said:

In this case how should I configure the clock to the IC.

Please explain the procedures on how should i configure the APLL and output clocks for my required outputs

The onboard IC can be configured with an I2C connection and with the TICS Pro GUI, or any I2C interface that enables communication with the device. We support interfacing I2C using a USB2ANY connection with an EVM, and other methods of interfacing with I2C are configured on a case-by-case basis by the designer. Once you have an I2C connection established, you can configure the APLL and clock output registers based on the LMK5C23208A Programmer's Guide. 

Abhishek Manoj said:

Instead of VDD_IN can i populate the external pull-up resistor for PD signal.

Yes, you should be able to use an external pull-up resistor for the PD# signal if you do not want to supply VDD_IN. Populating R1779 in your schematic should be sufficient to pull-up the PD# pin. 

Best,
Jaryd

Hi Jaryd,

Thanks for the reply.

Can we arrange a call to discuss the clock programming in more detail and get a clearer understanding of the configuration and implementation?

Are you available tomorrow or any day this week for a call between 7:00 PM and 8:30 PM IST?

Regards,

Abhishek