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LMX2572: SYNC timing relative to LOCK

John Roulston
Prodigy 40 points

Part Number: LMX2572

Two LMX2572s share a 100 MHz OSCin (one integer-N, one frac-N, 500 kHz offset), hopping 5 MHz steps every 30 µs with FCAL_EN=0 (pre-characterised VCO_SEL), FastLock, VCO_PHASE_SYNC_EN=1, SYNC pulsed at every step.

  1. Datasheet §7.3.11 includes "analog settling time of the PLL loop" in t1 — may SYNC be asserted at a fixed delay after the R0 write, before the loop has settled, with synchronization completing once it settles?
  2. If the loop slips a cycle after the SYNC pulse is latched, is output phase determinism preserved?
  3. If the channel divider is already in the correct state, does a SYNC pulse produce any output phase perturbation, or is it a true no-op?
  4. With MASH reset on every R0 write, what MASH_RST_COUNT constraint applies at a 30 µs step period?

 

  • 0
    TI__Guru** 122040 points

    Hi John,

    Phase sync requires FCAL_EN = 1. You can use full assist to change VCO parameters manually but need to keep FCAL_EN = 1 for phase sync. Changing frequency does not require programming of R0, you can hop very fast with full assist. 

    However, phase sync takes time. Whenever the device receives a sync pulse, the device will do a calibration then phase sync. MASH_RST_COUNT is used to setup a time duration for the device to complete calibration and phase sync. The time interval = MASH_RST_COUNT / fsm. fsm is the state machine clock = fosc / 2^CAL_CLK_DIV.

    If you want to do frequency hopping + phase sync, you cannot hop very fast because phase sync takes time. 

  • 0
    Prodigy 40 points

    Noel,

    Thanks for the steer. I can't use SYNC because it interferes with fast hopping. I can gain the coherence by other means. I have some more questions which need resolved to facilitate using the LMX2572.

    Configuration: LMX2572, 100 MHz shared OSCin, FCAL_EN=0 with pre-characterised VCO_SEL, FastLock enabled, no SYNC. Full-band VCO recalibration (FCAL_EN=1) is performed at the start of each measurement cycle, refreshing VCO_SEL at current temperature.

    Questions:

    1. FCAL_EN=0 hard gate: With FCAL_EN=0, is it guaranteed that no internal condition — VCO amplitude detect, lock-detect logic, supply transient, or sub-band boundary crossing — can autonomously trigger a calibration sequence? An unscheduled ~157 µs calibration on any tone during a measurement run would be fatal to our application.
    2. Sub-band boundary frequencies: What are the nominal VCO core boundary frequencies across the 3.2 – 6.4 GHz range? Characterisation data acceptable — we need to identify which of our 160 tones are near boundaries.
    3. Sub-band overlap and temperature drift: Is there designed overlap between adjacent sub-band tuning ranges, and if so what is the approximate overlap in MHz? What is the temperature coefficient of the boundary frequencies (MHz/°C)? We recalibrate at the start of each run; we need to know the within-run drift risk.
    4. FastLock at sub-band extremes: At the extreme of a sub-band's capacitor bank, Kv is reduced. Does this degrade FastLock settling time materially, and should we design the loop filter for worst-case Kv? What value should we assume?

    Please respond to all questions.

  • 0 in reply to John Roulston
    TI__Guru** 122040 points

    Hi John,

    A VCO calibration happens only when register R0 with FCAL_EN = 1 is programmed. If you are using full assist to switch VCO frequency, you can keep FCAL_EN = 1 because programming of R0 is not required. 

    To use full assist, we need to do a one-time calibration to create a look up table for the frequency of interest. Details is available here (www.ti.com/.../snaa336).

    There are 6 VCO in the chip, the boundary of adjacent VCO is overlapped. The approx. frequency range of each VCO is shown in the datasheet.

    The overlapping range varies from part to part as well as temperature. A calibration will pick the right spot for the frequency you want. The device is design in the way that the calibration data is valid over the entire temperature range. For example, if you do the calibration at -40C, the device remains lock without recalibration when the temperature has raised to 85C. So the one-time calibration does not need to do at different temperatures, we can do it a at room temperature, the data remains valid for other temperatures. Please note, because of part to part variation, each device must has its own LUT.

    Kvco changes over temperature and frequency, as a result, the loop filter bandwidth will change depending on the temperature and frequency. This will affect the VCO lock time. 

    In designing the loop filter, we usually use the Geometric Mean of Kvco.