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LMX2572: Cat3 phase sync not reliable

Alberto Burani
Prodigy 90 points

Part Number: LMX2572

Hello support team,

I'm facing a very strange issue whent I try to cat 3 sync 2 pll sharing the same clock.

the setup is the following: 2 pll sharing the same 100MHz clock and same sync signal. the timing between the sync signal and the rising edge of the clock is granted by a D FFlop triggering on the rising edge of the clock SN74LVC1G79DCKR.

On the output of the two PLL I have a mixer to detect the phase between them.

The output frequency is from 2400 to 2500MHz.

Problem description:

If I set my frequency between 2400 and 2475MHz the phase sync is reliable and i can see on the scope with infinite persistance the output of the mixer as a fixed level DC signal.

Yellow mixer output

red sync signal

image.png

If I set my frequency from 2478 to 2499MHz the the sync is no more reliable and the output of the mixer can assume 2 or more levels.

image.png

image.png

 

at 2500MHz the phase synch return reliable.

this is the data i'm sending:SCRIPT: Versione 1.0.0
SCRIPT: Avvio configurazione LMX2572 via FT232H + MCP23S17
Parametri ricevuti: ch=[3, 5] (2 elementi), pwr=34, frq=2499, pha=[0, 0], sw=1, gpiol0=None, gpiol1=None, sync=True, ms=master, eepromadd=None, eepromdata=None, eepromlen=None, verbose=True
SCRIPT: Dispositivi FTDI trovati: 1
  [0] description='C232HM-DDHSL-0' S/N='FTAKJ99C'
Adattatore selezionato: [0] 'C232HM-DDHSL-0' S/N='FTAKJ99C'
GPIOL0 (Sync) inizializzato a 0
GPIOL1 (CS Expander) inizializzato a 1
SCRIPT: Inizializzo i CS alti
SCRIPT: Configuro la scheda come master
SCRIPT: Invio Payload al PLL: 3
SCRIPT: PLL parameters calcolati: N=49, NUM=3528, DEN=3600, CHDIV=2, VCO=4998.0 MHz, OUTPUT=2499.0 MHz, ERROR=0.0 ppm
DEBUG: fase 0° -> phase_value 0 (0-3600)
SCRIPT: frame: 0x00 0x62 0x9E
SCRIPT: frame: 0x7C 0x00 0x00
SCRIPT: frame: 0x7B 0x00 0x00
SCRIPT: frame: 0x7A 0x00 0x00
SCRIPT: frame: 0x79 0x00 0x00
SCRIPT: frame: 0x78 0x00 0x00
SCRIPT: frame: 0x77 0x00 0x00
SCRIPT: frame: 0x76 0x00 0x00
SCRIPT: frame: 0x75 0x00 0x00
SCRIPT: frame: 0x74 0x00 0x00
SCRIPT: frame: 0x73 0x00 0x00
SCRIPT: frame: 0x72 0x78 0x02
SCRIPT: frame: 0x6A 0x00 0x07
SCRIPT: frame: 0x69 0x44 0x40
SCRIPT: frame: 0x68 0x13 0x88
SCRIPT: frame: 0x67 0x00 0x00
SCRIPT: frame: 0x66 0x00 0x00
SCRIPT: frame: 0x65 0x00 0x00
SCRIPT: frame: 0x64 0x13 0x88
SCRIPT: frame: 0x63 0x20 0x5C
SCRIPT: frame: 0x62 0x00 0x04
SCRIPT: frame: 0x61 0x00 0x00
SCRIPT: frame: 0x60 0x00 0x00
SCRIPT: frame: 0x56 0x00 0x00
SCRIPT: frame: 0x55 0xF7 0x00
SCRIPT: frame: 0x54 0x00 0x01
SCRIPT: frame: 0x53 0x00 0x00
SCRIPT: frame: 0x52 0x97 0x00
SCRIPT: frame: 0x51 0x00 0x00
SCRIPT: frame: 0x50 0x99 0x99
SCRIPT: frame: 0x4F 0x00 0x99
SCRIPT: frame: 0x4E 0x00 0x01
SCRIPT: frame: 0x4B 0x08 0x00
SCRIPT: frame: 0x4A 0x00 0x00
SCRIPT: frame: 0x49 0x00 0x3F
SCRIPT: frame: 0x48 0x00 0x01
SCRIPT: frame: 0x47 0x00 0x81
SCRIPT: frame: 0x46 0x8F 0xFF
SCRIPT: frame: 0x45 0x00 0x00
SCRIPT: frame: 0x3E 0x00 0xAF
SCRIPT: frame: 0x3C 0x03 0xE8
SCRIPT: frame: 0x3B 0x00 0x01
SCRIPT: frame: 0x3A 0x50 0x01
SCRIPT: frame: 0x39 0x00 0x20
SCRIPT: frame: 0x34 0x04 0x21
SCRIPT: frame: 0x2E 0x07 0xF0
SCRIPT: frame: 0x2D 0xC6 0x22
SCRIPT: frame: 0x2C 0x22 0x63
SCRIPT: frame: 0x2B 0x0D 0xC8
SCRIPT: frame: 0x2A 0x00 0x00
SCRIPT: frame: 0x29 0x00 0x00
SCRIPT: frame: 0x28 0x00 0x00
SCRIPT: frame: 0x27 0x0E 0x10
SCRIPT: frame: 0x26 0x00 0x00
SCRIPT: frame: 0x25 0x83 0x05
SCRIPT: frame: 0x24 0x00 0x31
SCRIPT: frame: 0x22 0x00 0x00
SCRIPT: frame: 0x1E 0x18 0xA6
SCRIPT: frame: 0x1D 0x00 0x00
SCRIPT: frame: 0x14 0x48 0x48
SCRIPT: frame: 0x13 0x27 0xB7
SCRIPT: frame: 0x11 0x00 0x96
SCRIPT: frame: 0x10 0x00 0x80
SCRIPT: frame: 0x0E 0x18 0x20
SCRIPT: frame: 0x0C 0x50 0x01
SCRIPT: frame: 0x0B 0xB0 0x28
SCRIPT: frame: 0x0A 0x10 0xF8
SCRIPT: frame: 0x09 0x00 0x04
SCRIPT: frame: 0x08 0x20 0x00
SCRIPT: frame: 0x07 0x00 0xB2
SCRIPT: frame: 0x06 0xC8 0x02
SCRIPT: frame: 0x05 0x30 0xC8
SCRIPT: frame: 0x01 0x08 0x08
SCRIPT: frame: 0x00 0x62 0x9C
SCRIPT: Invio Payload al PLL: 5
SCRIPT: PLL parameters calcolati: N=49, NUM=3528, DEN=3600, CHDIV=2, VCO=4998.0 MHz, OUTPUT=2499.0 MHz, ERROR=0.0 ppm
DEBUG: fase 0° -> phase_value 0 (0-3600)
SCRIPT: frame: 0x00 0x62 0x9E
SCRIPT: frame: 0x7C 0x00 0x00
SCRIPT: frame: 0x7B 0x00 0x00
SCRIPT: frame: 0x7A 0x00 0x00
SCRIPT: frame: 0x79 0x00 0x00
SCRIPT: frame: 0x78 0x00 0x00
SCRIPT: frame: 0x77 0x00 0x00
SCRIPT: frame: 0x76 0x00 0x00
SCRIPT: frame: 0x75 0x00 0x00
SCRIPT: frame: 0x74 0x00 0x00
SCRIPT: frame: 0x73 0x00 0x00
SCRIPT: frame: 0x72 0x78 0x02
SCRIPT: frame: 0x6A 0x00 0x07
SCRIPT: frame: 0x69 0x44 0x40
SCRIPT: frame: 0x68 0x13 0x88
SCRIPT: frame: 0x67 0x00 0x00
SCRIPT: frame: 0x66 0x00 0x00
SCRIPT: frame: 0x65 0x00 0x00
SCRIPT: frame: 0x64 0x13 0x88
SCRIPT: frame: 0x63 0x20 0x5C
SCRIPT: frame: 0x62 0x00 0x04
SCRIPT: frame: 0x61 0x00 0x00
SCRIPT: frame: 0x60 0x00 0x00
SCRIPT: frame: 0x56 0x00 0x00
SCRIPT: frame: 0x55 0xF7 0x00
SCRIPT: frame: 0x54 0x00 0x01
SCRIPT: frame: 0x53 0x00 0x00
SCRIPT: frame: 0x52 0x97 0x00
SCRIPT: frame: 0x51 0x00 0x00
SCRIPT: frame: 0x50 0x99 0x99
SCRIPT: frame: 0x4F 0x00 0x99
SCRIPT: frame: 0x4E 0x00 0x01
SCRIPT: frame: 0x4B 0x08 0x00
SCRIPT: frame: 0x4A 0x00 0x00
SCRIPT: frame: 0x49 0x00 0x3F
SCRIPT: frame: 0x48 0x00 0x01
SCRIPT: frame: 0x47 0x00 0x81
SCRIPT: frame: 0x46 0x8F 0xFF
SCRIPT: frame: 0x45 0x00 0x00
SCRIPT: frame: 0x3E 0x00 0xAF
SCRIPT: frame: 0x3C 0x03 0xE8
SCRIPT: frame: 0x3B 0x00 0x01
SCRIPT: frame: 0x3A 0x50 0x01
SCRIPT: frame: 0x39 0x00 0x20
SCRIPT: frame: 0x34 0x04 0x21
SCRIPT: frame: 0x2E 0x07 0xF0
SCRIPT: frame: 0x2D 0xC6 0x22
SCRIPT: frame: 0x2C 0x22 0x63
SCRIPT: frame: 0x2B 0x0D 0xC8
SCRIPT: frame: 0x2A 0x00 0x00
SCRIPT: frame: 0x29 0x00 0x00
SCRIPT: frame: 0x28 0x00 0x00
SCRIPT: frame: 0x27 0x0E 0x10
SCRIPT: frame: 0x26 0x00 0x00
SCRIPT: frame: 0x25 0x83 0x05
SCRIPT: frame: 0x24 0x00 0x31
SCRIPT: frame: 0x22 0x00 0x00
SCRIPT: frame: 0x1E 0x18 0xA6
SCRIPT: frame: 0x1D 0x00 0x00
SCRIPT: frame: 0x14 0x48 0x48
SCRIPT: frame: 0x13 0x27 0xB7
SCRIPT: frame: 0x11 0x00 0x96
SCRIPT: frame: 0x10 0x00 0x80
SCRIPT: frame: 0x0E 0x18 0x20
SCRIPT: frame: 0x0C 0x50 0x01
SCRIPT: frame: 0x0B 0xB0 0x28
SCRIPT: frame: 0x0A 0x10 0xF8
SCRIPT: frame: 0x09 0x00 0x04
SCRIPT: frame: 0x08 0x20 0x00
SCRIPT: frame: 0x07 0x00 0xB2
SCRIPT: frame: 0x06 0xC8 0x02
SCRIPT: frame: 0x05 0x30 0xC8
SCRIPT: frame: 0x01 0x08 0x08
SCRIPT: frame: 0x00 0x62 0x9C
SYNC: impulso GPIOL0 di 10 ms generato
SCRIPT: Invio Fase 0° al PLL: 3
SCRIPT: Invio Fase 0° al PLL: 5

 

this is  the schematic:

image.png

Do you have any idea of where to look at?

Thank you

 

 

  • 0
    Intellectual 405 points

    Hi Experts,

    I have the same issue on our board.

    Do you have any indication on what will be the problem?

    Please reply because this is a blocking point on our develpment!

    Thanks.

  • 0 in reply to Alessandro Spinetti1
    TI__Guru** 119910 points

    Hi There,

    I have no idea why problem happened after 2475MHz.

    After sync, could you do a register read back on register R110, R111 and R112?

    BTW, register 0x22 bit 4 should be =1. 

  • 0 in reply to Noel Fung
    Prodigy 90 points

    Thank for your feedback,

    Regarding register 0x22 the was a bug in our test software, now it is fixed

    following is the readback of the registers:

    R124 (0x7C): 0x0000
    R123 (0x7B): 0x0000
    R122 (0x7A): 0x0000
    R121 (0x79): 0x0000
    R120 (0x78): 0x0000
    R119 (0x77): 0x0000
    R118 (0x76): 0x0000
    R117 (0x75): 0x0000
    R116 (0x74): 0x0000
    R115 (0x73): 0x0000
    R114 (0x72): 0x7802
    R113 (0x71): 0x0000
    R112 (0x70): 0xFAB4
    R111 (0x6F): 0x0143
    R110 (0x6E): 0x0C88
    R109 (0x6D): 0x9D7D
    R108 (0x6C): 0x00A1
    R107 (0x6B): 0x8801
    R106 (0x6A): 0x0007
    R105 (0x69): 0x4440
    R104 (0x68): 0x1388
    R103 (0x67): 0x0000
    R102 (0x66): 0x0000
    R101 (0x65): 0x0000
    R100 (0x64): 0x1388
    R99 (0x63): 0x205C
    R98 (0x62): 0x0004
    R97 (0x61): 0x0000
    R96 (0x60): 0x0000
    R95 (0x5F): 0x0000
    R94 (0x5E): 0x0000
    R93 (0x5D): 0x0000
    R92 (0x5C): 0x0000
    R91 (0x5B): 0x0000
    R90 (0x5A): 0x0000
    R89 (0x59): 0x0000
    R88 (0x58): 0x0000
    R87 (0x57): 0x0000
    R86 (0x56): 0x0000
    R85 (0x55): 0xF700
    R84 (0x54): 0x0001
    R83 (0x53): 0x0000
    R82 (0x52): 0x9700
    R81 (0x51): 0x0000
    R80 (0x50): 0x9999
    R79 (0x4F): 0x0099
    R78 (0x4E): 0x0001
    R77 (0x4D): 0x0000
    R76 (0x4C): 0x000C
    R75 (0x4B): 0x0800
    R74 (0x4A): 0x0000
    R73 (0x49): 0x003F
    R72 (0x48): 0x0001
    R71 (0x47): 0x0081
    R70 (0x46): 0x8FFF
    R69 (0x45): 0x0000
    R68 (0x44): 0x03E8
    R67 (0x43): 0x0000
    R66 (0x42): 0x01F4
    R65 (0x41): 0x0000
    R64 (0x40): 0x1388
    R63 (0x3F): 0x0000
    R62 (0x3E): 0x00AF
    R61 (0x3D): 0x00A8
    R60 (0x3C): 0x03E8
    R59 (0x3B): 0x0001
    R58 (0x3A): 0x5001
    R57 (0x39): 0x0020
    R56 (0x38): 0x0000
    R55 (0x37): 0x0000
    R54 (0x36): 0x0000
    R53 (0x35): 0x0000
    R52 (0x34): 0x0421
    R51 (0x33): 0x0080
    R50 (0x32): 0x0080
    R49 (0x31): 0x4180
    R48 (0x30): 0x03E0
    R47 (0x2F): 0x0300
    R46 (0x2E): 0x07F0
    R45 (0x2D): 0xC622
    R44 (0x2C): 0x2263
    R43 (0x2B): 0x0000
    R42 (0x2A): 0x0000
    R41 (0x29): 0x0000
    R40 (0x28): 0x0000
    R39 (0x27): 0x0E10
    R38 (0x26): 0x0000
    R37 (0x25): 0x8305
    R36 (0x24): 0x0032
    R35 (0x23): 0x0004
    R34 (0x22): 0x0010
    R33 (0x21): 0x1E01
    R32 (0x20): 0x05BF
    R31 (0x1F): 0xC3E6
    R30 (0x1E): 0x18A6
    R29 (0x1D): 0x0000
    R28 (0x1C): 0x0488
    R27 (0x1B): 0x0002
    R26 (0x1A): 0x0808
    R25 (0x19): 0x0624
    R24 (0x18): 0x071A
    R23 (0x17): 0x007C
    R22 (0x16): 0x0001
    R21 (0x15): 0x0409
    R20 (0x14): 0x4848
    R19 (0x13): 0x27B7
    R18 (0x12): 0x0064
    R17 (0x11): 0x0096
    R16 (0x10): 0x0080
    R15 (0x0F): 0x060E
    R14 (0x0E): 0x1820
    R13 (0x0D): 0x4000
    R12 (0x0C): 0x5001
    R11 (0x0B): 0xB028
    R10 (0x0A): 0x10F8
    R9 (0x09): 0x0004
    R8 (0x08): 0x2000
    R7 (0x07): 0x00B2
    R6 (0x06): 0xC802
    R5 (0x05): 0x30C8
    R4 (0x04): 0x0A43
    R3 (0x03): 0x0782
    R2 (0x02): 0x0500
    R1 (0x01): 0x0808
    R0 (0x00): 0x6298

  • 0 in reply to Alberto Burani
    TI__Guru** 119910 points

    Hi There,

    I don't need the read back of all registers, I only need R110, R111 and R112, they represent the calibration data.

    Whenever a sync is triggered, the device will do a calibration followed by synchronization routine. After sync, would you read back the three register values of both LMX devices? Do a couple of sync and readback, purpose is to verify if the calibration data is consistent.

    In addition, you can try make MASH_SEED_EN = 0 as well as set MASH_RST_COUNT to a bigger number, e.g. 50000. 

  • 0 in reply to Noel Fung
    Prodigy 90 points

    I apologize for the misunderstanding.

    following are required registers configuration of 2 channels after the sync signal:

    CH7 CH8
      R112 (0x70): 0xFEAF   R112 (0x70): 0xFCB9
      R111 (0x6F): 0x014C   R111 (0x6F): 0x0143
      R110 (0x6E): 0x0C88   R110 (0x6E): 0x0C88

    Second try

    CH7 CH8
      R112 (0x70): 0xFEAE   R112 (0x70): 0xFCB9
      R111 (0x6F): 0x014C   R111 (0x6F): 0x0143
      R110 (0x6E): 0x0C88   R110 (0x6E): 0x0C88

    3rd try

    CH7 CH8
      R112 (0x70): 0xFEAE   R112 (0x70): 0xFCB9
      R111 (0x6F): 0x014C   R111 (0x6F): 0x0143
      R110 (0x6E): 0x0C88   R110 (0x6E): 0x0C88

    These are the values for channels 1-2 if it can help you:

    CH1 CH2
      R112 (0x70): 0xDEB4   R112 (0x70): 0xFEAF
      R111 (0x6F): 0x0155   R111 (0x6F): 0x014A
      R110 (0x6E): 0x0C88   R110 (0x6E): 0x0C88

    CH1 CH2
      R112 (0x70): 0xDEB6   R112 (0x70): 0xFEB0
      R111 (0x6F): 0x0154   R111 (0x6F): 0x014A
      R110 (0x6E): 0x0C88   R110 (0x6E): 0x0C88

    CH1 CH2
      R112 (0x70): 0xDEB6   R112 (0x70): 0xFEB0
      R111 (0x6F): 0x0154   R111 (0x6F): 0x0149
      R110 (0x6E): 0x0C88   R110 (0x6E): 0x0C88

    MASH_RST_COUNT was already set to 50000

  • 0 in reply to Alberto Burani
    Prodigy 90 points

    I apologize for the misunderstanding.

    following are required registers configuration of 2 channels after the sync signal:

    CH7 CH8
      R112 (0x70): 0xFEAF   R112 (0x70): 0xFCB9
      R111 (0x6F): 0x014C   R111 (0x6F): 0x0143
      R110 (0x6E): 0x0C88   R110 (0x6E): 0x0C88

    Second try

    CH7 CH8
      R112 (0x70): 0xFEAE   R112 (0x70): 0xFCB9
      R111 (0x6F): 0x014C   R111 (0x6F): 0x0143
      R110 (0x6E): 0x0C88   R110 (0x6E): 0x0C88

    3rd try

    CH7 CH8
      R112 (0x70): 0xFEAE   R112 (0x70): 0xFCB9
      R111 (0x6F): 0x014C   R111 (0x6F): 0x0143
      R110 (0x6E): 0x0C88   R110 (0x6E): 0x0C88

    These are the values for channels 1-2 if it can help you:

    CH1 CH2
      R112 (0x70): 0xDEB4   R112 (0x70): 0xFEAF
      R111 (0x6F): 0x0155   R111 (0x6F): 0x014A
      R110 (0x6E): 0x0C88   R110 (0x6E): 0x0C88

    CH1 CH2
      R112 (0x70): 0xDEB6   R112 (0x70): 0xFEB0
      R111 (0x6F): 0x0154   R111 (0x6F): 0x014A
      R110 (0x6E): 0x0C88   R110 (0x6E): 0x0C88

    CH1 CH2
      R112 (0x70): 0xDEB6   R112 (0x70): 0xFEB0
      R111 (0x6F): 0x0154   R111 (0x6F): 0x0149
      R110 (0x6E): 0x0C88   R110 (0x6E): 0x0C88

    MASH_RST_COUNT was already set to 50000

    this is the Sync signal timing:

    blue: clock

    red: synch signal (D FlipFlop input)

    yellow: clocked sync signal (D FlipFlop output, LMX2572Input)

    the oscin rising edge happens 6.6ns after the rising edge of sync signal

  • 0 in reply to Alberto Burani
    Prodigy 90 points

    A further question: do you think it could have sense to change the CHDIV register to 128 or 256, to have the possibility to read the signals of two channel with an oscilloscope?

    Thank you

  • +1 in reply to Alberto Burani
    TI__Guru** 119910 points

    Hi There,

    The readback data looks normal.

    Yes, we need to use a scope to verify if the phases are indeed deterministic.

    According to you register setting, MASH_RST_COUNT is 36863 or 368.63µs. Try make it longer to see if that helps.

  • 0 in reply to Noel Fung
    Prodigy 90 points

    Thank for your help.

    I've increased the MASH_RST_COUNT and now the phase sync process seems to be reliable.

    As you can see after the sync signal (red) the output of the phase detector takes all the times the same value.

    After sending the phase shift command the output of the phase detector reach its maximum value (1.75V) so both signals are in phase