Part Number: LMK5C23208A
Hello TI,
We wish to filter a 1PPS input to OUT0 using ZDM to DPLL3. Furthermore, we wish to subsequently use this filtered 1PPS output to SYNC all output clocks derived from PLL3.
Please could you confirm whether this SYNC triggered from OUT0 is directly possible via an internal mechanism or whether it would be necessary to externally route OUT0 to a GPIO in order to trigger SYNC via hardware pin.
Hi Bernhard,
There is no need to route external clock signals from output to input, as the zero-delay feedback clock from OUT0 is routed internally to the device. This SYNC from OUT0 will be present on all other clocks sourcing from DPLL3 without the need to externally route OUT0. What could be left is channel-to-channel skew, but any output sourced from DPLL3 will be synchronized to OUT0 1-PPS with the same phase relationship.
Best,
Jaryd
Hello Jaryd,
Just to be clear: Is it therefore possible via this mechanism to ensure that clock phases are aligned at the (output) 1PPS instant, so that all PLL3-derived clocks have their active edges aligned with the 1PPS OUT0 active edge (ignoring channel-to-channel skew for the moment)? Something like this (clocks in image below shown as SE with +ve active edge just for illustration, assume all derived from PLL3):
If so, what TICS Pro settings are pertinent in order to enable this, please?
