Other Parts Discussed in Thread: LMK00105, LMK00804B, LMK00101, CDCLVC1310, LMK1C1102
We have a timing-critical clock/sync distribution application and would appreciate some clarification on a few points, or indeed get your recommendation on a better solution, if one exists!
We have two potential SYNC clock sources and would like a 2:1 Single-Ended MUX solution, so we can route one or other of those signals to a sensor, with low jitter. Unfortunately it seems that 2:1 Single-Ended low jitter MUX solutions are hard to come by!
The signals involved range from a few kHz to 100 MHz and are 1.8 V single-ended, specifically from either:
- a low jitter clock buffer output (~1V/ns output slew rate, Renesas 5PB1102CMGI8 part which cannot unfortunately be changed).
- or an FPGA I/O output.
We've narrowed potential options down to LMK00105, LMK00101, LMK00804B and CDCLVC1310 (although the 10x outputs seem a bit over the top!)
We've also considered a solution with 2x additional clock buffers, each with an output enable feature and the outputs tied together, though it doesn't seem possible to find suitable buffers with Hi-Z outputs when disabled.
LMK00804B
1. Single-ended input amplitude
Initially this device looked promising, but in Section 7.7 (LVCMOS / LVTTL DC Characteristics), the LVCMOS_CLK input specifies VIH(min) = 2.0 V
Given that our clock sources are 1.8 V LVCMOS, does this mean that a 1.8 V clock is not guaranteed/supported on the LVCMOS_CLK input?
I came across the following E2E thread:
In that discussion, it appears the user changed their input signal from 3.3 V to 1.8 V and the device continued to operate, which prompted some questions regarding the supported input levels and recommended configurations?
2. Recommended bias network
In Figure 12, the driven input has a 100R resistor to VDD and a 100R resistor to GND.
With a 1.8 V source, this presents a relatively heavy load (~18 mA sink current when the source drives LOW). Our clock buffer doesn't specify a max sink/source current.
LMK00101/LMK00105
3. Single-ended input amplitude
The datasheets specify a single-ended input voltage swing: VI_SE = 0.3 V to 2.0 V
Presumably a 0 V to 1.8 V clock would be considered a valid single-ended input signal for the CLK/nCLK input pair?
LMK00101/LMK00105/LMK00804B
4.Input slew rate requirement
The datasheets recommends a (differential) input slew rate of ≥ 2 V/ns
Our clock buffer datasheet suggests approximately 1.08 V/ns slew rate. Would this single-ended input be expected to operate correctly with the LMK00101/LMK00105/LMK00804B?
Additionally, is the 2 V/ns figure a functional requirement for correct operation, or primarily a recommendation to achieve the specified additive jitter performance? The aforementioned TI forum post alludes to this being a requirement?
In another TI forum post, I noticed someone being recommended to precede the clock fanout buffer with an LMK1C1102 LVCMOS Clock Buffer, to achieve higher slew rates. Would that be a suggestion here?
5. Timing performance with single-ended 1.8 V sources
Do you have any characterisation data, application notes, or guidance regarding additive jitter performance when the LMK00101/LMK00105/LMK00804B are driven from a single-ended 1.8 V source rather than a differential source?
Our goal is to determine whether either device can be used directly with 1.8 V SE clock/sync sources while maintaining good timing performance, or whether level translation / a different configuration would be recommended.
Thank you for your help!
Robin
