LMX2594: LMX2594 related issues

Part Number: LMX2594

Hello,

The customer has been able to achieve phase synchronization of multiple LMX2594 chips. However, a new anomaly has occurred during use. When monitoring the output of four clocks using an oscilloscope, there is a probability that the relative phase relationship of the sine signals output by the four LMX2594 chips may change, and both integer and decimal modes may occur.


Reference frequency and phase detection frequency: 10MHz -->PLL -->100MHz, sine wave. 100MHz is provided to 4 LMX2594 chips as reference through a passive power divider.


Four LMX2594 chips with the same frequency configuration have been tested as follows:
1. Repeatedly configuring VCO automatic calibration, locking, configuring phase synchronization register, and sending SYNC signal will result in the above abnormalities;
2. Repeatedly sending sync pulses to 4 pieces of 2594 will also result in the above-mentioned abnormalities;
3. After sending the SYNC signal, repeat the core, band, and amplitude readings 300 times. Both core and band remain stable and unchanged; There is a slight change in amplitude, which is not significantly related to whether the phase is synchronized or not.


The sync signal is shown below:
The sync signal is generated using the same source 10MHz clock as LMX2594, with a pulse time of 10ms. The four LMX2594s use four 100MHz channels obtained from a power divider as a reference.  

Thanks.

  • Hi There,

    Do you have a plot showing the timing of SYNC pulse vs the 100MHz ref clock to LMX devices? Is this timing same on all LMX devices?

    Could you share your LMX2594 configuration?

    After calibration, VCO parameters (core, band, amplitude) would not change, we should get the same values on every readback.

  • Hi Noel,

    SYNC is distributed through FPGAs, where one FPGA is divided into two FPGAs, each of which is connected to two LMX2594 chips.


    At present, it can be seen that after configuring the same frequency point on four LMX2594 chips and repeatedly sending sync, the output phase of one of the four LMX2594 chips will randomly change. If it is the timing of sync, it should be more concentrated, or at least affect two of them, which is inconsistent with the current phenomenon.


    According to the manual description, sync will trigger VCO calibration, which affects the VCO band and amplitude values. I would like to know how to use sync without affecting these values?


    Furthermore, based on our current analysis of the issue, apart from the impact of VCO vibration, is there any other possibility that after each sync, there may be a random change in the output phase of one of the four LMX2594 chips?


    Use Partial Assist to configure, the configuration process is as follows:
    1) Calculate the PLL_N value and write it to the R36 register.
    2) Select the VCO-SEL value based on the configured frequency and write it to the R20 register.
    3) Calculate the value of VCO-CAPTRL_STRT and write it to the R78 register.
    4) Calculate the value of VCO-DACISETSET-STRT and write it to the R17 register.
    5) Set the calibration bit triggered by RO register bit3 to 1.

    Thanks.

  • Hi There,

    To brainstorm the problem, I still need the information I have asked previously.

    In addition, after sync, would you read back the VCO parameters for each device? 

  • Hi Noel,

    The configuration file of LMX2594 is attached, including initialization configuration and configuration after frequency point modification to 8.5G. Please help answer the question. Thanks.

    0x0    0x241a
    0x0    0x2418
    0x4b  0x800
    0x46  0xc350
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    0x13 0x27b7
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    0x0a 0x10d8
    0x09 0x604
    0x08 0x2000
    0x07 0x40b2
    0x04 0xa43
    0x01 0x808
    0x00 0x2418
    delay 10ms
    0x00 0x2418
    
    频点默认配置成9.5G
    0x00  0x2418
    0x25  0x300
    0x22  0x0
    0x24  0x5f
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    0x43  0x0
    0x42  0x1f4
    0x41  0x0
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    0x3d  0xa8
    0x3c  0x0
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    0x3a  0x1001
    0x39  0x20
    0x38  0x0
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    0x2d  0xc8df
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    0x22  0x0
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    0x14  0xd048
    0x4e  0x6d
    0x11  0x113
    0x2a  0x0
    0x2b  0x0
    0x1f  0x3ec
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    0x2d  0xc8df
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    0x1d  0x318c
    0x1c  0x488
    0x1b  0x2
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    0x18  0x71a
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    0x0e  0x1e70
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    0x0c  0x5001
    0x0b  0x18
    0x0a  0x10d8
    0x09  0x604
    0x08  0x2000
    0x07  0x40b2
    0x06  0xc802
    0x05  0xc8
    0x04  0xa43
    0x03  0x642
    0x02  0x500
    0x01  0x808
    0x00  0x6418
    频点修改为8.5G配置
    0x70  0x0
    0x6f   0x0
    0x6e  0x0
    0x6d  0x0
    0x6c  0x0
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    0x6a  0x0
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    0x53  0x0
    0x52  0x0
    0x51  0x0
    0x50  0x0
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    0x4e  0x3
    0x4d  0x0
    0x4c  0xc
    0x4a  0x0
    0x49  0x3f
    0x48  0x1
    0x47  0x81
    0x46  0xc350
    0x45  0x0
    0x44  0x3e8
    0x43  0x0
    0x42  0x1f4
    0x41  0x0
    0x40  0x1388
    0x3f  0x0
    0x3e  0x322
    0x3d  0xa8
    0x3c  0x0
    0x3b  0x1
    0x3a  0x1001
    0x39  0x20
    0x38  0x0
    0x37  0x0
    0x36  0x0
    0x35  0x0
    0x34  0x820
    0x33  0x80
    0x32  0x0
    0x31  0x4180
    0x30  0x300
    0x2f  0x300
    0x2e  0x7fd
    0x2d  0xc8df
    0x2c  0x1fa3
    0x2b  0x1f4
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    0x28  0x0
    0x27  0x3e8
    0x26  0x0
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    0x22  0x0
    0x24  0x55
    0x14  0xc048
    0x4e  0x35
    0x11  0xf6
    0x2a  0x0
    0x2b  0x0
    0x1f  0x3ec
    0x4b  0x800
    0x2d  0xc8df
    0x1e  0x318c
    0x1d  0x318c
    0x1c  0x488
    0x1b  0x2
    0x1a  0xdb0
    0x19  0xc2b
    0x18  0x71a
    0x17  0x7c
    0x16  0x1
    0x15  0x401
    0x13  0x27b7
    0x12  0x64
    0x11  0x12c
    0x10  0x80
    0x0f  0x64f
    0x0e  0x1e70
    0x0d  0x4000
    0x0c  0x5001
    0x0b  0x18
    0x0a  0x10d8
    0x09  0x604
    0x08  0x2000
    0x07  0x40b2
    0x06  0xc802
    0x05  0xc8
    0x04  0xa43
    0x03  0x642
    0x02  0x500
    0x01  0x808
    0x00  0x6418

  • Hello,

    Please help analyze the problem. Thanks.

  • HI There,

    I checked the 9.5GHz configuration, it looks fine. This is an integer channel, input/output phase is deterministic even without synchronization. I cannot think of any reason why the phases between the four devices are not consistent. Do you have the plot showing the phases difference?