Part Number: LMX2572LP
Other Parts Discussed in Thread: LMX2572
Hi,
We use LMX2572 in full‑assist mode with MUXout = lock detect. We hop through N frequencies (e.g., N=201). We always wait for LD high before starting the next hop. Normally we capture N rising edges on LD. Occasionally, we capture only N‑1 edges – one hop seems to produce no low‑to‑high transition.
Configuration:
- fpd = 100 MHz
- LD_DLY = 300 (which gives 12 µs delay)
- LD_TYPE = 1 (VCO calibration + Vtune check)
- Dwell time after each lock = 10 µs
Questions:
- Is it possible that during a hop the LD pin stays high (never goes low) and the device still reports lock?
- What is the minimum guaranteed low‑pulse width of LD during a hop?
- Do LD_TYPE or LD_DLY affect this low‑pulse behavior?
We want to confirm whether this could be a chip‑internal issue before debugging our FPGA sampling. Thanks.
