SPI_CLK input slew rate for CDCE62002, CDCE62005

Shahzad Malik97479

Intellectual 295 points

Other Parts Discussed in Thread: CDCE62002, CDCE62005

I am trying to determine the SPI CLK input slew rate specifications for the CDCE62002 and CDCE62005 clock synthesizers.

Also does any inputs include hysteresis?

over 13 years ago

0 Fritz over 13 years ago

TI__Expert 4150 points

Hi Shahzad,

the input slew rate requirements can be determined based on the setup and hold time requirements in table 5 of the CDCE62002. Ultimately you need to meet the VIH and VIL condition on SPI_MISO and SPI_LE when SPI_CLK latches.

The SPI_CLK input incorporates hysteresis (table 1 pin description).

An application note on SPI data transfers can be found here: http://e2e.ti.com/support/clocks/m/videos__files/180965.aspx

Best regards, Falk Alicke

Clock & timing

Clock & timing forum

SPI_CLK input slew rate for CDCE62002, CDCE62005