Part Number: LMX2594
Hi,
on category 3, the clock inputs of two PLLs has a fixed skew between them, and the sync pulses have a correct setup times before their clocks (>3ns), but not simulatanous, will the two PLLs outputs be with a same phase diff for each rerun?
what are the minimal requirements:
clocks can be with a fixed non zero skew?
sync pulses must be simulatanous or may be any skew after clock , still with sufficient setup time?
thanks ahead,
Yaacov.