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LMK05318B: Minimum DPLL loop bandwidth for LMK05318B?

John Ackermann
Prodigy 130 points

Part Number: LMK05318B

What's the minimum bandwidth the DPLL can be programmed to in the LMK05318B?  Using the TICS Pro program I was able to configure both 0.3 and 0.1 Hz bandwidths, but when doing an Allan Deviation stability measurement the results of the two are virtually identical, leading me to believe that the 0.1 Hz setting is beyond what can actually be programmed.

Also, the ADEV plot indicates that at 0.3 Hz the bandwidth is actually quite a bit narrower than that -- the ADEV "knee" occurs at about 60 seconds rather than the 3 seconds or so I would expect. 

So two questions:  1.  What is the minimum bandwidth one can program?  2.  Is the actual bandwidth more complex than the simple BW value plugged into the configuration tool?

Thanks!lmk_bw_comparison_adev.png

  • 0
    TI__Genius 16750 points

    Hi John, 

    The LMK05318B DPLL BW should be able to go down to 1mHz. Could you send over the .tcs configurations that you were testing with for each bandwidth setting? We have some calculators which can plot the predicted transfer function from LMK05318B's digital loop filter. 

  • 0 in reply to Connor Lewis
    Prodigy 130 points

    Here are the TCS files for the 0.3 Hz and 0.1 Hz bandwidths.  Thanks for reviewing!bw0p1hz_ref8844582.tcsbw0p3hz_ref8844582.tcs

  • 0 in reply to John Ackermann
    TI__Genius 16750 points

    Hi John, 

    Looking at the configs you attached, it does seem that the effective bandwidth is much higher than TICS Pro is indicating. For example, this is the simulated filter response for your 0.3Hz BW config: 

    I think there may be a limitation when calculating the DPLL filter parameters if the BW is below a certain ratio when compared to the TDC frequency. For example, we usually see <1Hz BWs used for a 1Hz TDC frequency, and TDC frequencies in the MHz range usually have a filter BW on the order of 10-1000Hz. Next week I can look into this more to see if it's possible to get a true ~0.1Hz BW with an ~8MHz reference frequency. 

    On another note, in your configs it seems that fastlock is enabled. This will temporarily increase the DPLL BW for a certain period of time during lock acquisition to improve the lock time. At the beginning of your measurements, are you sure that you're measuring the steady-state loop behavior? It might be worth testing with fastlock disabled just to make sure this isn't impacting the measurements.