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LMK5B12212EVM: EVM 1PPS REF DPLL Lock

Ralv Holmsen
Prodigy 10 points

Part Number: LMK5B12212EVM
Other Parts Discussed in Thread: LMK5B12212

Hi,

I'm currently evaluating the LMK5B12212 for one of our products. I'm using TICS Pro to configure the device, but I'm having issues getting the DPLL to lock to a 1 ppm reference. 

I've tried a few different output frequencies, but ended up using 4MHz out so I can easily see the APLL lock vs the built-in 48MHz reference. The final output frequencies are not important at this point, I just need it to work. As for the calculations I've been using the standard setup for the most part (as per EVM board).

I am using a 3.0 V referecnce at 1 Hz using an AWG (Square wave). The rise time is 25ns and the jitter should be in a few hundreds of ps, though I have not verified this. I suspect this should be good enough for evaluating the chip. I'm currently using my own instruments and private computer so I can show you the setup/share configuration files if required.

As aforementioned I've tried a few different setups, and I have in general palyed around with the TICS tool. I've in some instances been able to get a DPLL lock, but it has only lasted a few seconds. By referencing the status flags I've in some cases gotten the frequency lock to uncheck (not replicable), but I've never gotten the phase lock flag to uncheck - even though I've visually confirmed a phase lock (still only for a few seconds). Currently I am unable to replicate this even though I'm using a similar configuration. I suspect there is something wrong with my DPLL configuration, but I cannot figure it out.

I therefore ask you if you have any recommendations on how to proceed. I've read "The Debug Guide for Network Synchronizers (Digital and Analog Phase-Locked Loops)", but I am still unable to get this feature to work properly. Attached is the HexRegisterValues.txt

Best regards

  • 0
    TI__Genius 16750 points

    Hi Ralv, 

    Thanks for including a detailed summary and for attaching your register programming values. Could you also please attach your .tcs configuration file? This includes some user-input fields that aren't saved in the register map (ex: desired input/output frequencies) which can be helpful for evaluating the configuration. 

    I see that you mentioned that you went through the debug guide, could you also share your findings from that? In general, it's best practice to first ensure that the XO input is healthy and the APLL is successfully locking before troubleshooting the DPLLs. I would also recommend double checking the reference validation settings to make sure that the LMK5B considers the 1pps reference to be "valid" so the DPLL can attempt to lock to it. 

  • 0 in reply to Connor Lewis
    Prodigy 10 points

    Thank you for the prompt reply Lewis.

    I'm currently stuck on 2.5.2 - Debug DPLL Frequency Lock. I get a valid XO and REF, the values in TICS pro 'Inputs/DPLL Frequency' seems reasonable. I've tried widening the frequency validation thresholds without any lock, which may be a clue. Even after setting it to unreasonable values. I'm having a bit of a trouble uploading a screenshot of my status registers (hopefully it works), but the LOPL_DPLL1 and LOFL_DPLL1 are both set. Otherwise the status registers seem fine (REF_VALID_STATUS set, REF_FDET_STATUS and REF_PH_STATUS cleared). Changing the reference frequency also does uncheck REF_VALID_STATUS - Changing it back sets it.

    The .tcs is attached

    playground.tcs

  • 0 in reply to Ralv Holmsen
    TI__Genius 16750 points

    Thanks for sending over your config file, I don't see anything obvious that would prevent the DPLL from locking. Early next week I can try this out on my setup to see if I can replicate the same behavior. In the meantime, can you also try reading back APLL1_NUM_STAT when the DPLL is attempting to lock to the 1pps input? You should see the num stat value is constantly updating to keep the VCO locked to the reference input. Ideally, it should be somewhat close to the default APLL numerator value. If it has a very large delta that could indicate that the 1pps reference has a large frequency error compared to the 48MHz TCXO.