LMK04228: Clock generator selection

I noticed that the LMKD device is available only up to an operating temperature of 85°C.
Could you please suggest if there is:
An automotive-grade (AEC-Q100 qualified) equivalent,
An EP (Enhanced Product) version, or
A pin-compatible device that supports an extended operating temperature range up to 125°C?
Our application requires operation up to 125°C, so any suitable recommendation would be greatly appreciated.
Thank you for your support.

Hi Nishant,

Unfortunately, we do not have any automotive grade differential oscillators. What might work instead would be one of our automotive grade oscillators, like the CDC6C-Q1, being sent through a SN65LVDS9638.

Thanks,

Michael

Hello TI Team,

Thank you for recommending the CDC6C-Q1 for my application. I have a few follow-up questions regarding the clock architecture and interface for driving a high-speed pipeline ADC.

Application Details

• ADC Supply (AVDD): 1.8 V

• Required Clock Frequency: 30 MHz (Fixed)

• Clock Output Required: LVDS

• Application: High-speed ADC clock

• Preferred Devices: AEC-Q100 qualified 

1. LVCMOS to LVTTL Interface

As suggested, the CDC6C-Q1 provides an LVCMOS output, and the SN65LVDS9638 accepts an LVTTL-compatible input.

Could you please clarify the following?

• Is it acceptable to directly connect the LVCMOS output of the CDC6C-Q1 to the input of the SN65LVDS9638?

• Will this interface have any impact on the quality of the LVDS clock output, such as additional jitter, duty-cycle distortion, propagation delay, or any degradation in clock performance?

• Are there any recommended PCB layout guidelines or termination recommendations to obtain the best clock performance with this combination?

2. Alternative Clock Architecture

I also came across the SiTime SiT9396/SiT9397, which is an AEC-Q100 automotive-qualified fixed-frequency oscillator with a native LVDS output.

I understand this is not a TI device, but I would appreciate your opinion from an architectural perspective.

• Compared to the CDC6C-Q1 + SN65LVDS9638 solution, would an integrated LVDS oscillator generally provide any advantages in terms of:

  • Clock jitter

  • Phase noise

  • Signal integrity

  • PCB layout simplicity

  • Overall system performance

• Are there any advantages or disadvantages of using a separate LVCMOS clock generator followed by an LVDS driver versus a single integrated LVDS oscillator?

• For driving a high-speed ADC with a fixed 30 MHz LVDS clock, which architecture would you generally recommend?

3. 1.8 V LVDS Clock Source

My ADC operates with AVDD = 1.8 V and accepts an LVDS clock input.

If I use an LVDS oscillator operating from a 1.8 V supply, would this be a better approach than using a 3.3 V LVCMOS clock source followed by an LVDS driver?

Since both the clock source and the ADC would operate from the same 1.8 V supply, would this offer any advantages in terms of:

• Signal integrity

• Clock jitter

• Phase noise

• PCB routing

• Overall clock performance

Would this approach also eliminate the need for any 3.3 V to 1.8 V voltage conversion while still meeting the ADC LVDS input requirements?

4. 3.3 V to 1.8 V Clock Conversion

If I use a 3.3 V LVCMOS clock source and need to interface it with a 1.8 V clock domain, is there any recommended method other than using a dedicated level translator or clock buffer?

For evaluation and prototype testing, is it possible to implement a simple discrete circuit on the bench using basic analog or discrete components (such as resistors, MOSFETs, BJTs, or comparators) to perform this voltage conversion while maintaining good clock integrity?

If not, could you please explain why a dedicated clock translation device is preferred over a discrete implementation for high-speed clock signals?

If TI has any recommended application notes or reference circuits for this type of clock-level conversion, I would appreciate your guidance.

Thank you for your continued support. I look forward to your recommendations and technical guidance.

Best Regards,
Nishant Gupta

Hi Nishant,

Low on BW today. I will get to you tomorrow.

Thanks,

Michael

I have currently ordered the CDC6C oscillator for evaluation. The available device is configured for a 125 MHz output. For my application, I intend to use the FPGA to divide this clock down to 30 MHz or 15 MHz.

At present, I do not have a PCB designed with the 125 MHz oscillator footprint. Therefore, my plan is to perform the initial evaluation by mounting the CDC6C on an SMD-to-DIP adapter and using it for bench testing.

Could you please advise whether this is an acceptable approach for evaluating the oscillator? Additionally, I would appreciate your recommendations on the design practices, test setup, layout precautions, power supply decoupling, grounding, signal integrity, and measurement techniques that should be followed to obtain results that closely represent the performance of a properly designed PCB.

Hi Nishant,

For the purpose of bench testing, that is fine, although the performance will be better with the part soldered to the board and routed with an impedance matched trace. 

The CDC6CEVM (https://www.ti.com/tool/CDC6CEVM) provides a reference for appropriate layout. See the user's guide for more information.

Thanks,

Michael