LMK01801: Question about SYNC

One More Question, if ClockOut7 (LVCMOS) in Bank A is set (via SPI) to power down then power up again, will the Clk_in  to CLK_out delay change or not?

According to the block diagram, it seems the in-out delay should be constant that does not change under the same condition, is that correct? I like to know the delay value variation range over power off and on.  I mean, the same configuration, temperature and the same part.

Thanks,

Terry

Hi Terry,

Terry Liu70 said:

Assume both banks on LMK01801 are configured and synchronized. If I adjust digital delay over SPI and re-send SYNC1 during run time, will this operation affect outputs from Bank0?

This will only affect Bank1.

Terry Liu70 said:

According to the block diagram, it seems the in-out delay should be constant that does not change under the same condition, is that correct? I like to know the delay value variation range over power off and on.  I mean, the same configuration, temperature and the same part.

This is correct, we specify a typical value of 2.25ns. 

Thanks,

Michael