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LMK04002B EVAL ERROR in input frequency

Hello...

I am evaluating the LMK04002B using the EVB. In the National clock design tool I can put any frequency in the input and using the proper relationship in PLL1 (R and N counters) I got to "lock" with the input frequency, for example, using a 122.88 MHz VCXO in PLL1, putting 12.288 MHz in the input frequency and setting  R=1 and N=10 I got to lock the VCXO. But in the board LMK04002BEVAL I cannot lock with this same frequencies... I just got to lock using 122.88MHz in the input (the same frequcny of default VCXO) and "relation" 1 to 1 in R and N counters. Why? Why I can configure any frequency in the designs tool, but i cannot do it in a real world, I mean, in the EVB?

in the quick start guide of the LMK04002BEVAL is written: ..."Connect a reference clock from a signal generator or other source. Exact frequency depends on programming. Default modes use a 122.88 MHz reference"...

I tried to configure other frequencies, but only lock with 122.88MHz.

thank you very much!

 

  • Hello Fernando,

    In real life you should be able to get LMK04002B to lock to any frequency as long as it is within specification.  My guess is that you are using a signal generator to provide a clock input reference and that the slew rate presented to the CLKin input is too low as a minimum of 0.15 V/ns is specified for the CLKin.

    Note that a 0 dBm 12.288 MHz sine wave has a 20 to 80% slew rate of 0.023 V/ns and a 0 dBm 122.88 MHz sine wave has a 20 to 80% slew rate of 0.23 V/ns slew rate.  Please confirm the slew rate you are providing to the LMK04002BEVAL clock input.  It is possible to lock the LMK04002B device with less than 0.15 V/ns... increasing the power of a 12.288 MHz signal from a signal generator may do the trick.

     > Please advise if your still having difficulty locking PLL1 and slew rate is in the specified range.

    Also, for intended performance, if the phase detector frequency is changed - the loop filter should be updated for intended performance.  I.e. the evaluation board is designed to operate with an PLL1 N = 120, meaning the phase detector frequency should be 1.024 MHz no matter the input frequency.  As such the PLL1 R for a 12.288 MHz signal should be 12.  This will result in the same loop filter dynamics for PLL1.

      - The NCDT will design for the largest possible phase detector frequency because it is a simple matter to re-program the PLL1 R for a lower phase detector frequency, while sometimes it may not be obvious what the maximum PDF will be.

      - Also, high PDF frequencies allow better PLL performance.  This is especially important for PLL2... but not as critical for PLL1 because typically the PLL1 loop bandwidth is designed to be narrow to attenuate input jitter.  A narrow loop bandwidth will minimize the phase noise contribution from the PLL and allow the external VCXO or crystal noise to dominate.

    Final note, loading the actual CLKin reference and VCXO phase noise profiles into NCDT allows the user to re-calculate the PLL loop filters using real world phase noise references for best integrated jitter performance, and allows the tool to provide the most accurate phase noise simulations.

    73,

    Timothy

  • Hello Timothy,

    Thank you very much, I was using a RF signal generator and I didn´t check the Slew rate specification. 

    I tested with a square wave and got to lock with frequencies of hundreds KHz. Thank you very much for helping!

    att.

     

     

    Fernando Henrique Cardoso

    Beam Diagnostics Group (DIG)

    Brazilian Synchrotron Light Laboratory (LNLS/CNPEM)

    Campinas - Brazil - P.O.Box 6192 - ZIP Code 13083-970

    Tel: +55 19 3512-3517  ou 3512-1144//// Cel phone: +55 19 82156023

    Fax: +55 19 3512-1004