Hello Folks,
We are working in a 4 channel High speed ADC board for 500 MHz of input signal (FMC standard).
The target is to achieve the best SNR possible (in practice best ENOB), for this, we need to provide
a very low jitter clock signal for the 4 ADC´s. We need to generate the main clock frequency of
117.5 MHz for ADC´s, locked with an external frequency of a 625 KHz (dirty). OK, any IC clock
distribution can generate this signal using a VCXO for jitter cleanning. Using 2 PLL architeture like
LMK family we can use the second PLL without problem.
But the question is:
Due to complicated reasons we need sometimes change the clock frequency a litle bit
(step of 10 or 15 Hz) in a range of less than 100 Hz. For example generate 117.500015 MHz,
117.500030 MHz or 117.500.100 MHz maximum.
How can I do that using LMK family or CDCE family?
Is it possible or need I use a frequency sinthetizer/fractional PLL?
