LMK04828: LMK04828 Lock Issue

Is your 10MHz input a sine wave? Sine wave slew rate for 10MHz is < 0.15V/ns minimum requirement for PLL1 input.

The 10 MHz input is a sine wave. It is input at LVPECL levels via a buffer.
CLKin1 is used.

There is no amplitude of a 10MHz sine wave which is compatible with both the input slew rate requirement and the maximum allowable input amplitude for the device. A minimum of 0.15V/ns is required (in practice, much greater is desirable, more like 2V/ns, for good phase noise performance at close-in offsets). For a single-ended sine wave, the maximum allowable amplitude is 3.1Vpp, or 1.65Vpk; sine wave slew rate is 2π * f * Vpk, which is only 0.1V/ns. For 0.15V/ns, a sine wave at 10MHz would need minimum 2.39Vpk amplitude (4.78Vpp), which greatly exceeds the absolute maximum ratings of the device. A clipped sine wave or LVPECL square wave is required. 

If the 10MHz input is not just at LVPECL levels, but at LVPECL slew rates as well, and there are still problems locking, next I'd check the loop stability. The loop filter components appear to be copied from the EVM. They are selected for the specific gain of the VCXO on the EVM, a Crystek CVHD-950 with about 2kHz/V gain. I can't identify the VCXO in the schematic image based on its identifier, but if it is a different VCXO, it likely has a different gain, which can affect the loop stability. Can you provide a part number and datasheet for that VCXO if public, or a pull range and over what voltage if not public?

VCXO=KPV-638BRD122.880MHz

Made by a Japanese manufacturer

 pull range=100ppm

voltage=3.3V

I apologize for the inconvenience, and I appreciate your assistance.

There was a clerical error, and I am correcting it.

VCXO=KPV-638BRD122.880MHz

Made by a Japanese manufacturer

 pull range=50ppm

voltage=3.3V

I apologize for the inconvenience, and I appreciate your assistance.