CDCLVC1104: Clock fanout timing limits for STM32H743 SAI outputs

Jonathan Reichardt

Part Number: CDCLVC1104
Other Parts Discussed in Thread: SN65LVDS31, , LMK1C1104

Hello,

We are selecting clock buffers for BCLK and frame sync in a modular audio system.

The source is an STM32H743 operating at 3.0 to 3.6 V, with GPIO speed setting 10 and I/O compensation enabled. Its datasheet specifies a maximum rise and fall time of 2.8 ns with a 30 pF load.

BCLK is 12.288 MHz or 6.144 MHz. Frame sync is 96 kHz or 48 kHz. The intended ambient temperature is -20 to +85 degrees C.

The proposed path is:

STM32 output -> local clock buffer -> SN65LVDS31 inputs.

Each clock-buffer output would drive one nearby SN65LVDS31 input through a short PCB trace with a series damping resistor.

CDCLVC1104 specifies a recommended input slew rate of 1 to 4 V/ns. The MCU edge-time specification does not establish that minimum slew rate.

Please clarify:

1. Are guaranteed minimum and maximum propagation delay and pulse-width distortion limits available for CDCLVC1104 at input slew rates below 1 V/ns? If no guaranteed timing applies, please confirm this.

2. Could LMK1C1104 provide an alternative? Please provide applicable minimum and maximum propagation delays for both rising and falling transitions, including the input-slew and output-load conditions. We would keep its supply within its specified 3.3 V range.

3. CDCLVC1104 specifies a maximum output transition time of 0.8 ns measured from 20 to 80 percent. The SN65LVDS31 timing fixture specifies generator rise and fall times of at most 1 ns. What measurement interval applies to that driver fixture? Can these specifications establish timing compatibility between the two devices?

4. Is a maximum SN65LVDS31 logic-input capacitance available for load calculation?

5. If neither clock buffer provides applicable guaranteed limits, which TI alternative would you recommend for this source, with specified minimum and maximum delay and pulse-width distortion?

We can adjust local placement and damping resistors. We need applicable electrical limits before selecting the parts.

Kind regards,
Jonathan Reichardt

20 days ago

0 Tristan Morris 9 days ago

TI__Prodigy 240 points

Hey Jonathan,

1.) No, we do not have a guarantee below 1V/ns, however assuming that the clock output from your MCU is swinging from 0-3V minimum, with a max rise time of 2.8ns, the slew rate is around 1.08V/ns.

2.) LMK1C can be an alternative to this device, we do not specify propagation delay of falling transitions, but we do have the propagation delay max of rising edges as well as the duty cycle.

2a.) Propagation delay: <2ns

2b.) Duty cycle is 45%-55%

3.) Could you clarify what you mean by "measurement interval"? This spec on the SN65 is also measured 20 to 80 percent on the output, but I don't see a minimum or maximum rise time or slew rate on the input.

4.) We do not spec a maximum for this, but either CDCLVC or LMK1C should be able to drive the input capacitance with no issue.

5.) Based on the data you provided, I think CDCLVC and LMK1C would both work for this case.

Thank you,

Tristan

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CDCLVC1104: Clock fanout timing limits for STM32H743 SAI outputs