Part Number: LMK04832
hi expert
Debugging status:
1. The FPGA was configured with LMK04832, PLL1 and PLL2 were successfully locked, and the DCLK output was normal.
2. The OSCout outputted the SYSREF waveform normally.
3. When the SCLK source was set to the device clock, the output was normal.
Problem Description:
1. When the SCLK source is set to "device clock", the output signal period and waveform are both correct. As shown in Figure 1.
2. When the SCLK source is set to "SYSREF", the output signal period is correct, but the waveform is distorted. As shown in Figure 2.
3. When using the SYSREF pulser for output, the signal is similar to the continuous SYSREF, as shown in Figure 3.
Figure 1.
Figure 2
Figure 3
Summary: OSCout successfully outputs SYSREF, but SCLK fails to output continuous SYSREF or pulse SYSREF. A preliminary judgment suggests that the possible cause might be some issues with SYSREF_MUX. Please help to check.
Here is my register configuration data.
000090
000000
000200
01003C
01010A
010200
010340
010420
010520
01060A
010711
01083C
01090A
010A00
010B40
010C20
010D20
010E0A
010F11
01103C
01110A
011200
011340
011420
011520
011607
0117C1
01183C
01190A
011A00
011B40
011C10
011D00
011E01
011F01
012008
01210A
012280
012340
012410
012500
012601
012700
01281E
01290A
012A00
012B40
012C10
012D00
012E01
012F01
01303C
01310A
013200
013340
013410
013500
013601
013701
013831
013903
013A00
013B78
013C00
013D08
013E03
013F05
014000
014100
014200
014351
014400
014500
014618
01471B
014813
014913
014A02
014B06
014C00
014D00
014EC0
014F7F
015001
015102
015200
015300
015401
015500
015601
015700
015801
015900
015A02
015B14
015C20
015D00
015E1E
015F0B
016000
016101
01624C
016300
016400
01650F
016958
016A20
016B00
016C00
016D00
016E13
017310
017700
016600
016700
01680F
055500
013900
0143D1
0143F1
0143D1
0144FF
014351
014352
013903
018300
