Hello: my customer has designed in the CDCM7005 into a system, and is having trouble seetting the output to /1. EAU is 50/yr, they will ultimately use the space grade version. regards, George Biner, Arrow FAE Los Angeles
CDCM7005 application:
- 50 MHz reference input
- 1.6 GHz VCXO
- P divider = 8
- N divider = 4
- All outputs configured for LVPECL
- Yn_MUX configured for divide by 1 (1.6 GHz output)
We are aware that we are configuring the CDCM7005 #2 above its maximum specified 1500 MHz output. However, the datasheet specifically states in footnote (7) on page 8 that the outputs can be configured above 1500 MHz with degraded performance. Figure 5 depicts differential output voltage swing up to 1950 MHz output.
We are configuring the CDCM7005 device #2 (1600MHz) with the following configuration data:
WORD-0: 0x4000.3000
WORD-1: 0x0000.007D
WORD-2: 0xD000.14F2
WORD-3: 0x0000.0027
( WORD-x: 0xMSB…..LSB For example, in Word-0, the 0x4 of the MSB refers to bits [28..31] with values [0010]. )
CDCM7005 configured as indicated above, presents a 800 MHz clock at its outputs (we’re expecting 1600 MHz). If we re-configure the Yn_MUX to any other divider, we get the expected output frequency. E.g., if we configure Yn_MUX to select the divide by 4 output, we get 400 MHz. If divide by 8 is selected, we get 200 MHz. If divide by 2 is selected, we get 800 MHz. But if divide by 1 is selected, we still get 800 MHz. Note that in all cases the CDCM7005 indicates it is locked, and the measured VCXO input to the device is a compliant 1600 MHz LVPECL clock.
With a 1600 MHz VCXO input, the CDCM7005 seems unwilling to be configured for the divide by 1 output. We’re stumped. Any ideas?
