Support,
Securaplane (Meggit) entered the following question on the TI suppot ste and has not received and answer. Please help. I have requested a schematic and layout. Let me know if you need any additional information.
****Excessive Jitter Using National's LMH1983 Video Clock Generator. Only using the differential Clkout1+/- output but currently no I2C access so all CLKouts enabled. Datasheet states: TIE Deterministic Jitter = 250 fs and TIE random jitter = 2.7ps. Using Tektronix MSO72004C oscope (20GHz-100GS/s) measured: TIE Deterministic Jitter = 692 fs and TIE random jitter = 203ps(see attached jpeg image RefClk_27MHZ_r1.jpg). The NO_LOCK output is asserted. PLL1 Mode is in GENLOCK and I have Hsync, Vsync and Field present. It appears that there's a slight time shift in the output clock around 400ps (see attached jpeg image RefCLK_27MHZ_r2.jpg). Currently setting up the I2C interface so I can shut down the other three VCOs and mask the NO_LOCK signals from PLL2-4. Could you please provide any debug tips for this problem? The final 3G HD-SDI signall has twice the amount of jitter thats allowed for SMPTE 424 specification****
Regards,
John Wiemeyer