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CDCE62005 Smart Mux Not Operating

StuartT
Prodigy 250 points
Other Parts Discussed in Thread: CDCE62005

Hi,

We’re still having problems with our CDCE62005, both on the eval card and also our own card. I’ve updated the Registers as suggested (see below)  which narrowed the loop bandwidth and reduced the phase margin. This provides a good signal, i.e. it’s within the expected tolerance, but now we have an issue with using the PRI as a source.

Reg 6        808e02a6

Reg 7        8d9bbde7

Supplying a 100MHz LVDS clock to the PRI inputs on the Eval card (with the LVDS bias jumpers fitted), Reg 8 indicates the PRI source has been detected (by looking at Reg 8). Removing this source, the eval card doesn’t revert back to AUX.

Similarly, on power-up (or EVM reset) with no external signal present, Reg 8 indicates AUX is used. Applying the external signal, it does not then use this (based on what Reg is reporting). Therefore it appears the SMART_MUX feature does not appear to be functioning fully.

The SMART_MUX is set to PRI -> SEC ->AUX via Reg 5(4:2)

Further to that, when using the external source, the PLL will not lock and the output frequency is outwith what's expected. So maybe the input is good enough to be detected, but not good enough to actually use?

Could the SEL_DEL1 and SEL_DEL2 settings not matching have an impact? With the Reg 7 value suggested by Matt (8D9BBDE7) in a previous post (Ref “CDCE62005 Frequency Inaccuracy”) the SEL_DEL1 and 2 values do not match). Also, Bit 24 (TESTMUX2) is not set as per the datasheet. What impact could this have?

Also, what are the implications of having a slower (than 1V/ ns) slew rate clock to PRI/ SEC inputs?

Thanks

Stuart

  • 0
    TI__Expert 4150 points

    Hi Stuart,

    please send me the GUI ini file with your exact settings, and also a screenshot of your GUI to cdce62005_inquiry@list.ti.com.

    Also, tell me the frequencies that you apply to each of the inputs, and what kind of signaling you use (CMOS, LVDS, PECL, signal swing, etc).

    If you use external loop filter, please send me component value.

     

    The SmartMux should be working - so I assume there is another setup issue.

    Also, is the device calibrating properly - is your loop filter stable (meaning phase margin, loop bandwidth, gamma are all in a reasonable range?)

     

    Concerning your last question, slower input rise times result into higher input jitter, which then becomes attenuated by the PLL loop configuration.

     

    Best regards. Falk Alicke