Hello guys...
We are design high performance data acquisition system with 4 channels and we need to provide a ultra low jitter signal these 4 125 MSPS ADC´s that will do undersampling in a signal of 500 MHz. We need to use a PLL to lock the reference signal of 0.625 MHz and the output signal to ADC´s will be 117.5 MHz. Besides generate a fixed frequency clock of 117.5 MHz we also need sometimes to change this frequency +- 50 Hz steps in a reange of 1 or 2 KHz. we know that is possible to tune a VCXO of +-20ppm Pulling range.
Many high performance clock distribution like CDCE72010 and LMK family have no possibility to generate this fine frequency tunning... I am considering to use a High performance PLL, for ex. LMX2541 but I guess the performance is poor compared with CDCE and LMK family, right?
So,my questions are:
How to compare the jitter performance or phase noise performance of LMX2541 and IC´s like CDCE and LMK? is the LMX2541 worst for this application?
It´s possible to do fine frequency tunning using CDCE72010 or LMK family (dozens of Hz step in few KHz range)?
VCXO is really the best option to provide best jitter performance to PLL or ADC clock?
It´s possible to use a External VCXO companyng LMX2541? in the datasheet they only mention possibility to use external VCO...
thanks in advance