layout of LMK04808

Hello,

I assume the loop filter in this question must be designed for PLL1 since it includes a VCXO.

I place loop filter / capacitors close to the VCXO.  The loop filter converts current to voltage.  The VCXO should have a stable voltage at Vtune input which can be best achieved by placing the loop filter close to the VCXO.

I do have some questions about the design... because you mention only one capacitor is used for the loop filter.  I typically find this only for wide loop bandwidth PLL2 loop filters, not for PLL1 loop filters which are typically designed for a narrow loop bandwidth.

 - Was this loop filter for PLL1 designed using the clock design tool?  The clock design tool attempts to minimize integrated RMS jitter when integrated across loop bandwidth.  If the phase noise profile of the CLKin reference is not loaded with a noisy reference, it is possible that the clock design tool will pick a larger loop bandwidth than 10 Hz to 500 Hz recommend for normal use case of PLL1.  You may consider re-designing the loop bandwidth for a lower value, for example 50 Hz, I expect values for both C1 and C2 will be provided in this case.  When using a narrow loop bandwidth, the VCXO will dominate the noise profile provided to the second PLL and jitter clean any possible noisy input reference.

      > You may redesign the PLL1 loop bandwidth by entering a low loop bandwidth and pressing "Calculate" button.  Or,

      > You may redesign the PLL1 loop bandwidth by entering the phase noise profile for your CLKin reference, then automatically recalculate loop filter using "Recommend Design and Calculate" button.

      > In some cases, after redesigning the first PLL loop filter the second PLL2 loop filter should be checked by automatically recalculating loop filter using "Recommend Design and Calculate" button for 2nd PLL loop filter.

      > Please see our video tutorials for usage of clock design tool at the clock design tool page. 

  - Often a 2nd order loop filter design includes two capacitors (C1 & C2) and one resistor (R2).  However in some cases the capacitance for C1 is so small it is eliminated (0 F).  Of course there will always be a C1 capacitance represented by parasitic trace capacitance and VCXO input capacitance.  This typically happens for loop filters for PLL2 when the loop bandwidth is very wide, but not for PLL1.  PLL1 loop bandwidths are traditionally designed very narrow.  10 Hz to 500 Hz for instance.

73,

Timothy

In addition to Timothy's feedback, make sure the sensitive loop filter (Vtune) signal path and loop filter (ground) return path are routed away from nearby circuits which could potentially inject noise/spurious components inside the PLL loop bandwidth and cause VCXO modulation.  Routing can be made easier by placing the IC, loop filter, and VCXO components in close proximity and with good orientation, and by keeping high-speed traces away from the sensitive loop filter nodes.

Best regards,
Alan