Hello,
My customer has a question about PLL_LOCK pin.
When reference clock does not exist, does PLL LOCK detect circuit work?
For your reference, my customer's register setting is as follows.
Word0 BIT30 MANAUT = 0 : They are using Manual Reference Clock Selection and always using SEC_REF.
Word1 BIT29 ADLOCK = 1 : They select Analog PLL_LOCK.
Word3 BIT2/3 Lock Window = 11 : Cycle slip.
Word3 BIT4/5 Lock Cycles = 01 : 64.
Word3 BIT6 CSLIP = 0
And they are observing the followings.
When they disable reference clock input, PLL_LOCK pin goes low and stays low at most CDCM7005s.
But PLL_LOCK pin goes low once and goes high again few seconds after at some CDCM7005.
So, the customer would like to know if PLL_LOCK always work properly even if reference clock input is not available, stays always low.
Best regards,
K.Hirano
